diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-01 14:52:12 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-02 18:56:37 -0700 |
| commit | ac9f0f37362901f2418d1059ad583405e20ce65c (patch) | |
| tree | d0e3b739d88e35259bcc9d707dae81146c8e1814 /chip/npcx/config_chip.h | |
| parent | 2b5acbc8135ab49c5a10344f5d134153f52c4d17 (diff) | |
| download | chrome-ec-ac9f0f37362901f2418d1059ad583405e20ce65c.tar.gz | |
cleanup: Clarify use of flash layout CONFIGs
Based on feedback from programmers, it's not clear when
config_std_internal_flash should be used, and when non-standard
chip-specific layouts need to be defined. Add clarity here with the
following changes:
- Explain in-depth the one config that config_std_internal_flash should
be used for.
- Move non-standard chip-level flash layout CONFIGs to their own new
chip-level file, config_flash_layout. All chips should either include
config_std_internal_flash.h OR define their own layout in their own
config_flash_layout.
Functionally, this change is a NOP.
BUG=chrome-os-partner:23796
TEST=`make buildall -j`
BRANCH=None
Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296527
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip.h')
| -rw-r--r-- | chip/npcx/config_chip.h | 38 |
1 files changed, 1 insertions, 37 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 3b39065220..be2e0c15a0 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -79,43 +79,7 @@ /* 128 KB alignment for SPI status registers protection */ #define CONFIG_FLASH_PHYSICAL_SIZE 0x40000 /* 256 KB Flash used for EC */ -/* No PSTATE; uses a real SPI flash */ -#undef CONFIG_FLASH_PSTATE - -/* Header support which is used by booter to copy FW from flash to code ram */ -#define NPCX_RO_HEADER - -/****************************************************************************/ -/* Define npcx flash layout. */ -/* Size of one firmware image in flash */ -#ifndef CONFIG_FW_IMAGE_SIZE -#define CONFIG_FW_IMAGE_SIZE (CONFIG_FLASH_PHYSICAL_SIZE / 2) -#endif - -/* The storage offset of ec.RO.flat which is used for CONFIG_CDRAM_ARCH */ -#define CONFIG_RO_STORAGE_OFF 0 -#ifdef NPCX_RO_HEADER -#define CONFIG_RO_HDR_MEM_OFF 0x0 -#define CONFIG_RO_HDR_SIZE 0x40 -/* RO firmware offset in flash */ -#define CONFIG_RO_MEM_OFF CONFIG_RO_HDR_SIZE -#else -#define CONFIG_RO_MEM_OFF 0x0 -#endif -#define CONFIG_RO_SIZE CONFIG_CDRAM_SIZE /* 96KB for RO FW */ -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE - -/* The storage offset of ec.RW.flat which is used for CONFIG_CDRAM_ARCH */ -#define CONFIG_RW_STORAGE_OFF CONFIG_FW_IMAGE_SIZE /* 128 KB alignemnt */ -/* RW firmware offset in flash */ -#define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF -#define CONFIG_RW_SIZE CONFIG_CDRAM_SIZE /* 96KB for RW FW */ - -#define CONFIG_WP_OFF CONFIG_RO_STORAGE_OFF -#define CONFIG_WP_SIZE CONFIG_FW_IMAGE_SIZE - -/****************************************************************************/ -/* Customize the build */ +#include "config_flash_layout.h" /* Optional features present on this chip */ #define CONFIG_ADC |