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| author | Mulin Chao <mlchao@nuvoton.com> | 2016-03-09 14:27:53 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-03-15 21:49:36 -0700 |
| commit | 3424deb4813365abbad0b02c5fb8c29dcc4ffc74 (patch) | |
| tree | 24e6aeea8adf5e1ffd2e7b9db15807a17d7c1c1c /chip/npcx/config_flash_layout.h | |
| parent | 750b4525da7c1336968b0d881e18571670ae307c (diff) | |
| download | chrome-ec-3424deb4813365abbad0b02c5fb8c29dcc4ffc74.tar.gz | |
npcx: Add 256KB alignment of RO & RW regions for npcx5m6g.
Since npcx5m6g has larger than 128 KB code ram for FW, the original
alignment between RO & RW regions isn't suitable for new chip.
Therefore, we add 256KB alignment of them for npcx5m6g.
In order to program the flash used by npcx5m6g, we add new board array,
BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout
ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g
and flash_npcx5m6g to program flash with different layout.
Modified sources:
1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for
npcx5m6g.
2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to
distinguish which flash layout ec used.
3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with
different layout.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/331903
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/npcx/config_flash_layout.h')
| -rw-r--r-- | chip/npcx/config_flash_layout.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index 22322271f0..065f4a3645 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -20,10 +20,19 @@ #define CONFIG_MAPPED_STORAGE_BASE 0x64000000 #undef CONFIG_FLASH_PSTATE +#if defined(CHIP_VARIANT_NPCX5M5G) #define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 #define CONFIG_EC_WRITABLE_STORAGE_OFF 0x20000 #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 +#elif defined(CHIP_VARIANT_NPCX5M6G) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#else +#error "Unsupported chip variant" +#endif /* Header support which is used by booter to copy FW from flash to code ram */ #define NPCX_RO_HEADER |