diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-09-19 11:37:19 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-09-28 23:26:17 -0700 |
| commit | dbf3c71b4578d0e0e743c247bfdf95fee11d1a9e (patch) | |
| tree | cb8daf7c0edc8c9aedb864b71594972dc9c90724 /chip/npcx/espi.c | |
| parent | 367e11ba28302292f125c8d108f60bae1a6fd002 (diff) | |
| download | chrome-ec-dbf3c71b4578d0e0e743c247bfdf95fee11d1a9e.tar.gz | |
npcx: espi: Fixed the bug which ec cannot enter deep sleep on npcx7.
In npcx7, we introduced a new bit, VWUPDW, in ESPISTS register to
indicate a Master-to-Slave VW signal was updated and the relevant WE
bit is 1. But there's no relevant IE bit in ESPIIE for VWUPDW, old
mechanism for clearing pending bits of ESPISTS will ignore this bit.
And ec cannot enter deep sleep anymore since this bit is set. This CL
fixed this bug by setting bit 17 of mask variable if ec is npcx7 series.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series.
Change-Id: I80c57d3c230e9d06ba134538ccdcd29f290bb7bf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/672183
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Diffstat (limited to 'chip/npcx/espi.c')
| -rw-r--r-- | chip/npcx/espi.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 11c3fc6a00..6731546db0 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -527,7 +527,15 @@ void espi_interrupt(void) int chan; uint32_t mask, status; +#if defined(CHIP_FAMILY_NPCX7) + /* + * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask + * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR. + */ + mask = NPCX_ESPIIE | (1 << NPCX_ESPISTS_VWUPDW); +#else mask = NPCX_ESPIIE; +#endif status = NPCX_ESPISTS & mask; while (status) { |