diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2016-10-11 11:59:32 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-10-11 23:01:37 -0700 |
| commit | d809d1614f0d9fd0b332c6046f8e2e66eb4adff6 (patch) | |
| tree | dbe6889ff9b18e697a4ead3562d686347b4de8e7 /chip/npcx/espi.c | |
| parent | da558fc83362c5f3270eab49c16d3a70653a3a4b (diff) | |
| download | chrome-ec-d809d1614f0d9fd0b332c6046f8e2e66eb4adff6.tar.gz | |
npcx: Enable VW's valid bits of SCI#/SMI# if no CONFIG_SCI_GPIO.
Enable valid bits of SCI#/SMI# of eSPI's VW if there's no CONFIG_SCI_GPIO
definition in board-level driver. This CL also fixed the order of VW
event bits in comments.
Modified sources:
1. espi.c: Enable valid bits of SCI#/SMI#.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make all; test nuvoton IC specific drivers
Change-Id: I8d094513284b4ed42c5c26fe1975d71bbf050aa4
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396618
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Diffstat (limited to 'chip/npcx/espi.c')
| -rw-r--r-- | chip/npcx/espi.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 938c479679..7d841362bb 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -58,7 +58,7 @@ struct vw_event_t { /* Default settings of VWEVMS registers (Please refer Table.43/44) */ static const struct vwevms_config_t espi_in_list[] = { - /*IDX EN ENPL ENESP IE VW Event Bit 3 -0 (M->S) */ + /* IDX EN ENPL ENESP IE VW Event Bit 0 - 3 (M->S) */ {0x02, 1, 0, 0, 0}, /* SLP_S3#, SLP_S4#, SLP_S5, Reserve */ {0x03, 1, 0, 1, 0}, /* SUS_STAT#, PLTRST#, ORST_WARN, Reserve */ {0x07, 1, 1, 1, 0}, /* HRST_WARN, SMIOUT#, NMIOUT#, Reserve */ @@ -69,11 +69,15 @@ static const struct vwevms_config_t espi_in_list[] = { /* Default settings of VWEVSM registers (Please refer Table.43/44) */ static const struct vwevsm_config_t espi_out_list[] = { - /*IDX EN ENPL ENCDR VDMASK VW Event Bit 3 -0 (S->M) */ - {0x04, 1, 0, 0, 0x0D}, /* PME#, WAKE#, Reserve, ORST_ACK */ - {0x05, 1, 0, 0, 0x0F}, /* SLV_BL_STS, ERR_NF, ERR_F, SLV_BL_DONE*/ - {0x06, 1, 1, 0, 0x0C}, /* HRST_ACK, RCIN#, SMI#, SCI# */ - {0x40, 1, 0, 0, 0x01}, /* Reserve, Reserve, Reserve, SUS_ACK# */ + /* IDX EN ENPL ENCDR VDMASK VW Event Bit 0 - 3 (S->M) */ + {0x04, 1, 0, 0, 0x0D}, /* ORST_ACK, Reserve, WAKE#, PME# */ + {0x05, 1, 0, 0, 0x0F}, /* SLV_BL_DNE, ERR_F, ERR_NF, SLV_BL_STS */ +#ifdef CONFIG_SCI_GPIO + {0x06, 1, 1, 0, 0x0C}, /* SCI#, SMI#, RCIN#, HRST_ACK */ +#else + {0x06, 1, 1, 0, 0x0F}, /* SCI#, SMI#, RCIN#, HRST_ACK */ +#endif + {0x40, 1, 0, 0, 0x01}, /* SUS_ACK, Reserve, Reserve, Reserve */ }; /* eSPI interrupts used in MIWU */ |