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authorScott Collyer <scollyer@google.com>2021-11-23 15:04:49 -0800
committerScott Collyer <scollyer@google.com>2021-11-23 15:04:49 -0800
commit817cf2223b0b33c91ca6e369b644cbc4d6c361e3 (patch)
treef698bbab73d87af25f9fdc2d49f50a0c25111a79 /chip/npcx/gpio-npcx9.c
parent6da8436a8ce04a7f88f80049a10638e1b8f6439d (diff)
parent0349a5b6d95308141754523708a2d11d8bacce4c (diff)
downloadchrome-ec-817cf2223b0b33c91ca6e369b644cbc4d6c361e3.tar.gz
Merge remote-tracking branch 'cros/main' into firmware-gwc-fsi
Change-Id: Id9b5b5cb1db7428cd9f12452d73842d8c1f2705a
Diffstat (limited to 'chip/npcx/gpio-npcx9.c')
-rw-r--r--chip/npcx/gpio-npcx9.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c
index f0ed529808..31ed4e62ac 100644
--- a/chip/npcx/gpio-npcx9.c
+++ b/chip/npcx/gpio-npcx9.c
@@ -52,13 +52,13 @@ DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
*/
#define GPIO_IRQ_FUNC(_irq_func, wui_int) \
-void _irq_func(void) \
+static void _irq_func(void) \
{ \
gpio_interrupt(wui_int); \
}
/* If we need to handle the other type interrupts except GPIO, add code here */
-void __gpio_host_interrupt(void)
+static void __gpio_host_interrupt(void)
{
if (IS_ENABLED(CONFIG_HOSTCMD_X86)) {
/* Pending bit 7 or 6 or 5? */
@@ -70,7 +70,7 @@ void __gpio_host_interrupt(void)
SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6);
return;
}
- if (IS_ENABLED(CONFIG_HOSTCMD_ESPI)) {
+ if (IS_ENABLED(CONFIG_HOST_INTERFACE_ESPI)) {
if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5)
&&
IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) {
@@ -97,7 +97,7 @@ static void set_rtc_host_event(void)
DECLARE_DEFERRED(set_rtc_host_event);
#endif
-void __gpio_rtc_interrupt(void)
+static void __gpio_rtc_interrupt(void)
{
/* Check pending bit 7 */
#ifdef CONFIG_HOSTCMD_RTC
@@ -110,7 +110,7 @@ void __gpio_rtc_interrupt(void)
#endif
gpio_interrupt(WUI_INT(MIWU_TABLE_0, MIWU_GROUP_4));
}
-void __gpio_cr_sin2_interrupt(void)
+static void __gpio_cr_sin2_interrupt(void)
{
#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 1)
/* Handle the interrupt from UART wakeup event */
@@ -133,7 +133,7 @@ void __gpio_cr_sin2_interrupt(void)
}
-void __gpio_wk1h_interrupt(void)
+static void __gpio_wk1h_interrupt(void)
{
#if defined(CONFIG_LOW_POWER_IDLE) && (CONFIG_CONSOLE_UART == 0)
/* Handle the interrupt from UART wakeup event */
@@ -154,7 +154,7 @@ void __gpio_wk1h_interrupt(void)
gpio_interrupt(WUI_INT(MIWU_TABLE_1, MIWU_GROUP_8));
}
-void __gpio_lct_interrupt(void)
+static void __gpio_lct_interrupt(void)
{
if (NPCX_WKPND(MIWU_TABLE_2, MIWU_GROUP_6) & LCT_WUI_MASK) {
NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) |= LCT_WUI_MASK;
@@ -195,7 +195,7 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3);
#endif
DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3);
DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3);
-#ifdef CONFIG_HOSTCMD_SHI
+#ifdef CONFIG_HOST_INTERFACE_SHI
/*
* HACK: Make CS GPIO P2 to improve SHI reliability.
* TODO: Increase CS-assertion-to-transaction-start delay on host to