diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2016-08-04 11:20:45 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-10 22:16:57 -0700 |
| commit | ef6e93dc1bbf92821c9d3ff149f691fbdad1c015 (patch) | |
| tree | 793e53f708df2537811314916ca00e43e269cb50 /chip/npcx/gpio.c | |
| parent | a625b710c3e4d64a659ae20682b85dd552657b6c (diff) | |
| download | chrome-ec-ef6e93dc1bbf92821c9d3ff149f691fbdad1c015.tar.gz | |
npcx: Add espi driver of npcx5mng for x86-based platform.
Add espi driver for x86-based platform which support espi interface such
as skylake and so on.
Added source:
1. espi.c: Add drivers which supports the utilities of peripheral and
virtual-wire channels so far.
2. espi.h: Add espi virtual-wire declaration for power sequence FW.
Modified sources:
1. lpc.c: Add interrupts and initialization steps for espi.
2. gpio.c: Add interrupt handler of espi reset.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: Ie80afe79d85aba47fc0b72898a8374c2898ec114
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/366181
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/gpio.c')
| -rw-r--r-- | chip/npcx/gpio.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index b5bf0f80c3..1d701203c7 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -786,18 +786,25 @@ void _irq_func(void) \ /* If we need to handle the other type interrupts except GPIO, add code here */ void __gpio_wk0efgh_interrupt(void) { -#ifdef CONFIG_LPC - /* Pending bit 7 or 6 ? */ +#if defined(CONFIG_LPC) || defined(CONFIG_ESPI) + /* Pending bit 7 or 6 or 5? */ if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 6) && IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 6)) { /* Disable host wake-up */ CLEAR_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); /* Clear pending bit of WUI */ - SET_BIT(NPCX_WKPCL(MIWU_TABLE_0 , MIWU_GROUP_5), 6); - } else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0 , MIWU_GROUP_5), 7) && - IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0 , MIWU_GROUP_5), 7)) + SET_BIT(NPCX_WKPCL(MIWU_TABLE_0, MIWU_GROUP_5), 6); + } +#ifdef CONFIG_ESPI + else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 5) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 5)) + espi_espirst_handler(); +#else + else if (IS_BIT_SET(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 7) && + IS_BIT_SET(NPCX_WKPND(MIWU_TABLE_0, MIWU_GROUP_5), 7)) lpc_lreset_pltrst_handler(); - else /* FW will jump into ISR again if other GPIOs' INT still issued */ +#endif + else #endif gpio_interrupt(NPCX_IRQ_WKINTEFGH_0); } |