diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-05-25 15:33:24 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-06-10 01:30:23 -0700 |
| commit | 206f1dd93b04b6240b079ef7af1fe97ae5f6bdd8 (patch) | |
| tree | 513f0f61235d50a61474895dec520eb384bec69c /chip/npcx/gpio.c | |
| parent | a08d004e97e3bd6fe232b5f050bad2c448f381c0 (diff) | |
| download | chrome-ec-206f1dd93b04b6240b079ef7af1fe97ae5f6bdd8.tar.gz | |
npcx: gpio: Lock VCC_RST# alternative bit of DEVALTA.
This CL locks VCC_RST# alternative bit, NO_VCC1_RST, of DEVALTA
in case the developers switch it to GPO77 unexpectedly by setting
VCC1_RST_LK bit in DEV_CTL4.
BRANCH=none
BUG=none
TEST=Use rw console command to make sure NO_VCC1_RST bit is
locked on npcx7_evb.
Change-Id: Ic7882ef1c8050c3daca85bd241d5368f009e4e2e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/522206
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/gpio.c')
| -rw-r--r-- | chip/npcx/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index 83c09f130e..01d47850ae 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -369,6 +369,8 @@ void gpio_pre_init(void) * for more information. It will be fixed in next chip. */ SET_BIT(NPCX_DEVCNT, 7); + /* Lock VCC_RST# alternative bit in case switch to GPO77 unexpectedly */ + SET_BIT(NPCX_DEV_CTL4, NPCX_DEV_CTL4_VCC1_RST_LK); #endif /* Pin_Mux for FIU/SPI (set to GPIO) */ |