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authorShawn Nematbakhsh <shawnn@chromium.org>2016-08-22 14:44:02 -0700
committerchrome-bot <chrome-bot@chromium.org>2016-08-23 15:36:30 -0700
commit8fd12a56f171ddc54158eace07df6b8cf79a7c3a (patch)
tree4646d94fa3e9dbca059260c6a9c47859186986b2 /chip/npcx/gpio.c
parent40a4bd1d639249abf0a5b0f71d79c486a890a1ad (diff)
downloadchrome-ec-8fd12a56f171ddc54158eace07df6b8cf79a7c3a.tar.gz
npcx: Don't enable GPIO interrupts by default
GPIO interrupts must first be enabled with a call to gpio_enable_interrupt() to prevent ISRs from being run before prerequiste modules are initialized. BUG=chrome-os-partner:56486 BRANCH=None TEST=Manual on kevin, stress test sysjump for ~1 hour (~700 sysjumps) without failure. Change-Id: Ia4006ef1b0c3218dfe5c92fde6713c10b0d22d2a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374020 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Diffstat (limited to 'chip/npcx/gpio.c')
-rw-r--r--chip/npcx/gpio.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index 1d701203c7..4e3b19e31c 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -472,7 +472,6 @@ static void gpio_interrupt_type_sel(uint8_t port, uint8_t mask, uint32_t flags)
NPCX_WKEDG(table, group) |= pmask;
/* Enable wake-up input sources */
- NPCX_WKEN(table, group) |= pmask;
NPCX_WKINEN(table, group) |= pmask;
/*
* Clear pending bit since it might be set
@@ -505,7 +504,6 @@ static void gpio_interrupt_type_sel(uint8_t port, uint8_t mask, uint32_t flags)
}
/* Enable wake-up input sources */
- NPCX_WKEN(table, group) |= pmask;
NPCX_WKINEN(table, group) |= pmask;
/*
* Clear pending bit since it might be set
@@ -682,10 +680,13 @@ void gpio_pre_init(void)
SET_BIT(NPCX_DEVALT(ALT_GROUP_1), NPCX_DEVALT1_NO_LPC_ESPI);
#endif
- /* Clear all pending bits of GPIOS*/
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
+ /* Clear all interrupt pending and enable bits of GPIOS */
+ for (i = 0; i < 2; i++) {
+ for (j = 0; j < 8; j++) {
NPCX_WKPCL(i, j) = 0xFF;
+ NPCX_WKEN(i, j) = 0;
+ }
+ }
/* No support enable clock for the GPIO port in run and sleep. */
/* Set flag for each GPIO pin in gpio_list */