diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-08-05 00:28:09 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-08-07 21:43:55 -0700 |
| commit | 9ab83ede1016637429ac66140d7c903a0dfaefd9 (patch) | |
| tree | 10e4493013c0a0dc1c631b71335c601e9deaba47 /chip/npcx/gpio.c | |
| parent | 1fac91707184ef5466148e5dbc3418704475e488 (diff) | |
| download | chrome-ec-9ab83ede1016637429ac66140d7c903a0dfaefd9.tar.gz | |
npcx: Adjust relative IRQ priorities for high-priority UART
Our UART interrupt must be able to preempt our SHI_CS interrupt,
otherwise console input may be lost. Adjust our relative IRQ priorities
to accommodate this.
BUG=chrome-os-partner:55920
BRANCH=None
TEST=Run `echo "kbpress 11 4 1" > /dev/pts/17` on kevin 200 times from
the recovery screen, verify that all input is received by the EC.
Change-Id: I36203511f5883272287ac22d0704098fbd933758
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/366622
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Diffstat (limited to 'chip/npcx/gpio.c')
| -rw-r--r-- | chip/npcx/gpio.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index edd9597aad..b5bf0f80c3 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -826,26 +826,26 @@ GPIO_IRQ_FUNC(__gpio_wk1f_interrupt , NPCX_IRQ_WKINTF_1); GPIO_IRQ_FUNC(__gpio_wk1g_interrupt , NPCX_IRQ_WKINTG_1); GPIO_IRQ_FUNC(__gpio_wk1h_interrupt , NPCX_IRQ_WKINTH_1); -DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 1); +DECLARE_IRQ(NPCX_IRQ_MTC_WKINTAD_0, __gpio_rtc_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTEFGH_0, __gpio_wk0efgh_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 2); #ifdef CONFIG_HOSTCMD_SPS /* - * HACK: Make CS GPIO P0 to improve SHI reliability. + * HACK: Make CS GPIO P1 to improve SHI reliability. * TODO: Increase CS-assertion-to-transaction-start delay on host to - * accommodate P1 CS interrupt. + * accommodate P2 CS interrupt. */ -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 0); -#else DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 1); +#else +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 1); -DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 1); +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 2); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 2); #undef GPIO_IRQ_FUNC |