diff options
| author | Ian Chao <mlchao@nuvoton.com> | 2015-07-09 14:53:00 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-25 01:22:32 +0000 |
| commit | 14bd917343489c09033f0f9c97e7951d5cb2aeec (patch) | |
| tree | 1722f9d92f5ffb2525eebec68f86b1aab06b3e71 /chip/npcx/gpio.c | |
| parent | 7de0037538bd0016c9202ad289655cbf4f4d90aa (diff) | |
| download | chrome-ec-14bd917343489c09033f0f9c97e7951d5cb2aeec.tar.gz | |
nuc:
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/npcx/gpio.c')
| -rw-r--r-- | chip/npcx/gpio.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index 34634943b3..51e3d844c8 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -551,20 +551,34 @@ void gpio_pre_init(void) int flags; int i, j; - uint32_t ksi_mask = (~((1<<KEYBOARD_ROWS)-1)) & KB_ROW_MASK; - uint32_t ks0_mask = (~((1<<KEYBOARD_COLS)-1)) & KB_COL_MASK; + uint32_t ksi_mask = (~((1<<KEYBOARD_ROWS)-1)) & KB_ROW_MASK; + uint32_t kso_mask = ((~((1<<KEYBOARD_COLS)-1)) + << CONFIG_KEYBOARD_KSO_BASE) & KB_COL_MASK; - /* Set necessary pin mux first */ +#ifdef CONFIG_KEYBOARD_COL2_INVERTED + kso_mask |= 1 << (CONFIG_KEYBOARD_KSO_BASE + 2); +#endif + + /* Set necessary pin mux to GPIO first */ /* Pin_Mux for KSO0-17 & KSI0-7 */ NPCX_DEVALT(ALT_GROUP_7) = (uint8_t)(ksi_mask); - NPCX_DEVALT(ALT_GROUP_8) = (uint8_t)(ks0_mask); - NPCX_DEVALT(ALT_GROUP_9) = (uint8_t)(ks0_mask >> 8); - NPCX_DEVALT(ALT_GROUP_A) |= (uint8_t)(ks0_mask >> 16); + NPCX_DEVALT(ALT_GROUP_8) = (uint8_t)(kso_mask); + NPCX_DEVALT(ALT_GROUP_9) = (uint8_t)(kso_mask >> 8); + NPCX_DEVALT(ALT_GROUP_A) |= (uint8_t)(kso_mask >> 16); /* Pin_Mux for FIU/SPI (set to GPIO) */ SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP); SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); + /* Pin_Mux for PWRGD */ + SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_NO_PWRGD); + + /* Pin_Mux for PECI */ +#ifndef CONFIG_PECI + SET_BIT(NPCX_DEVALT(0xA), NPCX_DEVALTA_NO_PECI_EN); +#endif + + /* Pin_Mux for LPC & SHI */ #ifdef CONFIG_SHI /* Switching to eSPI mode for SHI interface */ NPCX_DEVCNT |= 0x08; |