diff options
| author | CHLin <CHLIN56@nuvoton.com> | 2018-10-26 15:39:06 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-30 01:04:58 -0700 |
| commit | 36190da7c5b8ac47aefc8eaa9fb581b9b77bd26b (patch) | |
| tree | 68747ff0c584012c0d538d520fbcf1030ebd0784 /chip/npcx/gpio_chip-npcx7.h | |
| parent | 09a5e0a9398a1ca9e953969d5c10d3b60cda8eac (diff) | |
| download | chrome-ec-36190da7c5b8ac47aefc8eaa9fb581b9b77bd26b.tar.gz | |
npcx: gpio: fix bugs of low voltage level selection
This CL fixed the following bugs of low voltage support of GPIO:
1. fix the mismatch issue of low voltage support GPIOs when the mask
passed to gpio_low_voltage_level_sel() has multiple bits set.
(see more detail in the bug:118443060.)
The idea is to create a new function gpio_low_vol_sel_by_mask() to
iterate the match for each bit set in the mask.
i.e.
while (lv_mask) {
bit = get_next_bit(&lv_mask);
gpio_low_voltage_level_sel(p, bit, low_vol);
};
The second parameter of gpio_match()/gpio_low_voltage_level_sel is
also changed from "mask" to "bit" because of above modification.
2. It was observed that there are some errors of the low level mapping
table because the older datasheet we used to develop the driver is not
correct. After checking the latest datasheets of all EC sku, the low
level table should have the following modification:
- GPIO65 cannot support low level and should be removed.
- GPIO86 can support low level in all EC skus.
BRANCH=none
BUG=b:118443060
TEST=Add GPIO_SEL_1P8V flag in the ALTERNATE macros which have multiple
bits set in the mask field in npcx7_evb board. Flash the image and make
sure the warning message doesn't print and the related low level bits
are set.
Change-Id: I7aa23eb42dda178db34fe44a663df29757910a55
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1301674
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Diffstat (limited to 'chip/npcx/gpio_chip-npcx7.h')
| -rw-r--r-- | chip/npcx/gpio_chip-npcx7.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/chip/npcx/gpio_chip-npcx7.h b/chip/npcx/gpio_chip-npcx7.h index 7fe1ee41a3..c8e28c9ddb 100644 --- a/chip/npcx/gpio_chip-npcx7.h +++ b/chip/npcx/gpio_chip-npcx7.h @@ -442,7 +442,7 @@ #define NPCX_LVOL_CTRL_1_3 NPCX_GPIO(D, 0) #define NPCX_LVOL_CTRL_1_4 NPCX_GPIO(3, 6) #define NPCX_LVOL_CTRL_1_5 NPCX_GPIO(6, 4) -#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO(6, 5) +#define NPCX_LVOL_CTRL_1_6 NPCX_GPIO_NONE #define NPCX_LVOL_CTRL_1_7 NPCX_GPIO_NONE /* Low-Voltage GPIO Control 2 */ @@ -480,11 +480,7 @@ #define NPCX_LVOL_CTRL_3_7 NPCX_GPIO(C, 5) /* Low-Voltage GPIO Control 4 */ -#ifdef NPCX_PSL_MODE_SUPPORT -#define NPCX_LVOL_CTRL_4_0 NPCX_GPIO_NONE /* Remove 1.8V support since PSL */ -#else #define NPCX_LVOL_CTRL_4_0 NPCX_GPIO(8, 6) -#endif #define NPCX_LVOL_CTRL_4_1 NPCX_GPIO(C, 2) #define NPCX_LVOL_CTRL_4_2 NPCX_GPIO(F, 3) #define NPCX_LVOL_CTRL_4_3 NPCX_GPIO(F, 2) |