npcx: gpio: Add support for npcx7 series ec.

This CL includes:
1. Add gpio_chip-npcx5/7.h files and move all macro functions
   related to chip family to them. (Move wui macro func from
   gpio_wui.h to them.)
2. Replace alternative and low-voltage mapping table with macro
   function NPCX_ALT_TABLE and NPCX_LVOL_TABLE.
3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR.
4. Add gpio register definitions of npcx7 family in registers.h.
5. Add GPIO_LOCKED flag for lock functionality.

BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
     Build poppy board and upload FW to platform. No issues found.
     Passed validation for all GPIO functionalities on npcx5m6g
     and npcx796f evb.

Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481561
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

1 files changed, 47 insertions, 0 deletions

diff --git a/chip/npcx/gpio_chip.h b/chip/npcx/gpio_chip.h
new file mode 100644
index 0000000000..1595f6b20d
--- /dev/null
+++ b/chip/npcx/gpio_chip.h
@@ -0,0 +1,47 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_GPIO_CHIP_H
+#define __CROS_EC_GPIO_CHIP_H
+
+/* Macros to initialize the MIWU mapping table. */
+#define NPCX_WUI_GPIO_PIN(port, index) NPCX_WUI_GPIO_##port##_##index
+#define WUI(tbl, grp, idx) ((struct npcx_wui) { .table = tbl, .group = grp, \
+						.bit = idx })
+#define WUI_INT(tbl, grp)  WUI(tbl, grp, 0)
+
+/* Macros to initialize the alternative and low voltage mapping table. */
+#define NPCX_GPIO_NONE ((struct npcx_gpio) {.port = 0, .bit = 0, .valid = 0})
+#define NPCX_GPIO(grp, pin) ((struct npcx_gpio) {.port = GPIO_PORT_##grp, \
+							.bit = pin, .valid = 1})
+
+#define NPCX_ALT(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
+			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 0 })
+#define NPCX_ALT_INV(grp, pin) ((struct npcx_alt) {.group = ALT_GROUP_##grp, \
+			.bit = NPCX_DEVALT##grp##_##pin, .inverted = 1 })
+#define ALT(port, index, alt) { NPCX_GPIO(port, index), alt },
+
+#define NPCX_LVOL_CTRL_ITEMS(ctrl) { NPCX_LVOL_CTRL_##ctrl##_0, \
+				     NPCX_LVOL_CTRL_##ctrl##_1, \
+				     NPCX_LVOL_CTRL_##ctrl##_2, \
+				     NPCX_LVOL_CTRL_##ctrl##_3, \
+				     NPCX_LVOL_CTRL_##ctrl##_4, \
+				     NPCX_LVOL_CTRL_##ctrl##_5, \
+				     NPCX_LVOL_CTRL_##ctrl##_6, \
+				     NPCX_LVOL_CTRL_##ctrl##_7, }
+
+/*
+ * Include the MIWU, alternative and low-Voltage macro functions for GPIOs
+ * depends on Nuvoton chip series.
+ */
+#if defined(CHIP_FAMILY_NPCX5)
+#include "gpio_chip-npcx5.h"
+#elif defined(CHIP_FAMILY_NPCX7)
+#include "gpio_chip-npcx7.h"
+#else
+#error "Unsupported chip family"
+#endif
+
+#endif /* __CROS_EC_GPIO_CHIP_H */