Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

1 files changed, 31 insertions, 30 deletions

diff --git a/chip/npcx/header.c b/chip/npcx/header.c
index 0ba3ee59d6..2db7d9094c 100644
--- a/chip/npcx/header.c
+++ b/chip/npcx/header.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Copyright 2015 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,59 +16,60 @@
 #include "registers.h"
 
 /* Signature used by fw header */
-#define SIG_FW_EC           0x2A3B4D5E
+#define SIG_FW_EC 0x2A3B4D5E
 
 /* Definition used by error detection configuration */
-#define CHECK_CRC	    0x00
-#define CHECK_CHECKSUM	    0x01
-#define ERROR_DETECTION_EN  0x02
+#define CHECK_CRC 0x00
+#define CHECK_CHECKSUM 0x01
+#define ERROR_DETECTION_EN 0x02
 #define ERROR_DETECTION_DIS 0x00
 
 /* Code RAM addresses use by header */
 /* Put FW at the begin of CODE RAM */
-#define FW_START_ADDR  CONFIG_PROGRAM_MEMORY_BASE
+#define FW_START_ADDR CONFIG_PROGRAM_MEMORY_BASE
 
 /* TODO: It will be filled automatically by ECST */
 /* The entry point of reset handler (filled by ECST tool)*/
-#define FW_ENTRY_ADDR  0x100A8169
+#define FW_ENTRY_ADDR 0x100A8169
 
 /* Error detection addresses use by header (A offset relative to flash image) */
-#define ERRCHK_START_ADDR  0x0
-#define ERRCHK_END_ADDR    0x0
+#define ERRCHK_START_ADDR 0x0
+#define ERRCHK_END_ADDR 0x0
 
 /* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/
-#define FW_SIZE            CONFIG_RO_SIZE
+#define FW_SIZE CONFIG_RO_SIZE
 
 /* FW Header used by NPCX5M5G Booter */
 struct __packed fw_header_t {
-	uint32_t anchor;         /* A constant used to verify FW header       */
-	uint16_t ext_anchor;     /* Enable/disable firmware header CRC check  */
-	uint8_t  spi_max_freq;   /* Spi maximum allowable clock frequency     */
-	uint8_t  spi_read_mode;  /* Spi read mode used for firmware loading   */
-	uint8_t  cfg_err_detect; /* FW load error detection configuration     */
-	uint32_t fw_load_addr;   /* Firmware load start address               */
-	uint32_t fw_entry;       /* Firmware entry point                      */
+	uint32_t anchor; /* A constant used to verify FW header       */
+	uint16_t ext_anchor; /* Enable/disable firmware header CRC check  */
+	uint8_t spi_max_freq; /* Spi maximum allowable clock frequency     */
+	uint8_t spi_read_mode; /* Spi read mode used for firmware loading   */
+	uint8_t cfg_err_detect; /* FW load error detection configuration     */
+	uint32_t fw_load_addr; /* Firmware load start address               */
+	uint32_t fw_entry; /* Firmware entry point                      */
 	uint32_t err_detect_start_addr; /* FW error detect start address      */
-	uint32_t err_detect_end_addr;   /* FW error detect end address        */
-	uint32_t fw_length;      /* Firmware length in bytes                  */
-	uint8_t  flash_size;     /* Indicate SPI flash size                   */
-	uint8_t  reserved[26];   /* Reserved bytes                            */
-	uint32_t sig_header;     /* The CRC signature of the firmware header  */
-	uint32_t sig_fw_image;   /* The CRC or Checksum of the firmware image */
+	uint32_t err_detect_end_addr; /* FW error detect end address        */
+	uint32_t fw_length; /* Firmware length in bytes                  */
+	uint8_t flash_size; /* Indicate SPI flash size                   */
+	uint8_t reserved[26]; /* Reserved bytes                            */
+	uint32_t sig_header; /* The CRC signature of the firmware header  */
+	uint32_t sig_fw_image; /* The CRC or Checksum of the firmware image */
 } __aligned(1);
 
-__keep  __attribute__ ((section(".header")))
+__keep __attribute__((section(".header")))
 const struct fw_header_t fw_header = {
 	/* 00 */ SIG_FW_EC,
 	/* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h    */
-	/* 06 */ 0x04,   /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
-	/* 07 */ 0x03,   /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
-	/* 08 */ 0x00,   /* Disable CRC check functionality */
+	/* 06 */ 0x04, /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
+	/* 07 */ 0x03, /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
+	/* 08 */ 0x00, /* Disable CRC check functionality */
 	/* 09 */ FW_START_ADDR,
-	/* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */
+	/* 0D */ FW_ENTRY_ADDR, /* Filling by ECST tool with -usearmrst option
+				 */
 	/* 11 */ ERRCHK_START_ADDR,
 	/* 15 */ ERRCHK_END_ADDR,
-	/* 19 */ FW_SIZE,/* Filling by ECST tool */
-	/* 1D */ 0x0F,   /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
+	/* 19 */ FW_SIZE, /* Filling by ECST tool */
+	/* 1D */ 0x0F, /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
 	/* 1E-3F Other fields are filled by ECST tool or reserved         */
 };