nuc: Add SHI driver for arm-based platform in chip folder.

Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter

Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>

1 files changed, 72 insertions, 0 deletions

diff --git a/chip/npcx/header.c b/chip/npcx/header.c
new file mode 100644
index 0000000000..ff0c50eb3b
--- /dev/null
+++ b/chip/npcx/header.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Booter header for Chrome EC.
+ *
+ * This header is used by Nuvoton EC Booter.
+ */
+
+#include <stdint.h>
+#include "registers.h"
+#include "config_chip.h"
+
+/* Signature used by fw header */
+#define SIG_FW_EC           0x2A3B4D5E
+
+/* Definition used by error detection configuration */
+#define CHECK_CRC	    0x00
+#define CHECK_CHECKSUM	    0x01
+#define ERROR_DETECTION_EN  0x02
+#define ERROR_DETECTION_DIS 0x00
+
+/* Code RAM addresses use by header */
+#define FW_START_ADDR  CONFIG_CDRAM_BASE /* Put FW at the begin of CODE RAM   */
+
+/* TODO: It will be filled automatically by ECST */
+/* The entry point of reset handler (filled by ECST tool)*/
+#define FW_ENTRY_ADDR  0x100A8169
+
+/* Error detection addresses use by header (A offset relative to flash image) */
+#define ERRCHK_START_ADDR  0x0
+#define ERRCHK_END_ADDR    0x0
+
+/* Firmware Size -> Booter loads RO region after hard reset (16 bytes aligned)*/
+#define FW_SIZE            CONFIG_RO_SIZE
+
+/* FW Header used by NPCX5M5G Booter */
+struct __packed fw_header_t {
+	uint32_t anchor;         /* A constant used to verify FW header       */
+	uint16_t ext_anchor;     /* Enable/disable firmware header CRC check  */
+	uint8_t  spi_max_freq;   /* Spi maximum allowable clock frequency     */
+	uint8_t  spi_read_mode;  /* Spi read mode used for firmware loading   */
+	uint8_t  cfg_err_detect; /* FW load error detection configuration     */
+	uint32_t fw_load_addr;   /* Firmware load start address               */
+	uint32_t fw_entry;       /* Firmware entry point                      */
+	uint32_t err_detect_start_addr; /* FW error detect start address      */
+	uint32_t err_detect_end_addr;   /* FW error detect end address        */
+	uint32_t fw_length;      /* Firmware length in bytes                  */
+	uint8_t  flash_size;     /* Indicate SPI flash size                   */
+	uint8_t  reserved[26];   /* Reserved bytes                            */
+	uint32_t sig_header;     /* The CRC signature of the firmware header  */
+	uint32_t sig_fw_image;   /* The CRC or Checksum of the firmware image */
+} __aligned(1);
+
+__attribute__ ((section(".header")))
+const struct fw_header_t fw_header = {
+	/* 00 */ SIG_FW_EC,
+	/* 04 */ 0x54E1, /* Header CRC check Enable/Disable -> AB1Eh/54E1h    */
+	/* 06 */ 0x04,   /* 20/25/33/40/50 MHz -> 00/01/02/03/04h             */
+	/* 07 */ 0x03,   /* Normal/Fast/Rev/D_IO/Q_IO Mode -> 00/01/02/03/04h */
+	/* 08 */ 0x00,   /* Disable CRC check functionality */
+	/* 09 */ FW_START_ADDR,
+	/* 0D */ FW_ENTRY_ADDR,/* Filling by ECST tool with -usearmrst option */
+	/* 11 */ ERRCHK_START_ADDR,
+	/* 15 */ ERRCHK_END_ADDR,
+	/* 19 */ FW_SIZE,/* Filling by ECST tool */
+	/* 1D */ 0x0F,   /* Flash Size 1/2/4/8/16 Mbytes -> 01/03/07/0F/1Fh   */
+	/* 1E-3F Other fields are filled by ECST tool or reserved         */
+};