npcx: i2c: Add support for npcx7 series ec

This CL added support for 8 i2c controllers and 11 i2c ports in
npcx7 series ec. we also added i2c-npcx5/7.c and moved the functions
related to chip family to them. (Such as i2c_port_to_controller(),
i2c_select_port() and so on.) Note the layout and bit position of i2c
registers which are accessed in these functions are irregular between
npcx5 and npcx7. We think abstracting them from i2c.c is easier to
maintain.

In this CL, we also modified the checking rule for I2C_PORT_COUNT in
task.h in order to prevent compiler error. So far, the ECs besides
stm32 only use TASK_EVENT_I2C_IDLE to wait for i2c hardware completes
its job. Put (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) checking rule
for all ECs seems not suitable.

It also includes
1. Remove useless NPCX_I2C_PUBIT macro function.
2. Remove useless NPCX_PWDWN_CTL_COUNT in registers.h.
3. Add CGC_OFFSET_I2C2 and CGC_I2C_MASK2 to power down the other 4 i2c
   controllers of npcx7 ec.

BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
     Build poppy board and upload FW to platform. No issues found.
     All 8 i2c controllers and 10 ports (npcx796f supports PSL.) passed
     i2c stress tests on npcx796f evb.

Change-Id: I2b5076d21bcd0f8d17fd811cad2ff7bd200b112a
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/487541
Reviewed-by: Randall Spangler <rspangler@chromium.org>

1 files changed, 47 insertions, 0 deletions

diff --git a/chip/npcx/i2c-npcx5.c b/chip/npcx/i2c-npcx5.c
new file mode 100644
index 0000000000..6b78fd53f9
--- /dev/null
+++ b/chip/npcx/i2c-npcx5.c
@@ -0,0 +1,47 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* I2C module driver depends on chip series for Chrome EC */
+
+#include "i2c.h"
+#include "i2c_chip.h"
+#include "registers.h"
+#include "util.h"
+
+/*****************************************************************************/
+/* IC specific low-level driver depends on chip series */
+
+int i2c_port_to_controller(int port)
+{
+	if (port < 0 || port >= I2C_PORT_COUNT)
+		return -1;
+
+	return (port == NPCX_I2C_PORT0_0) ? 0 : port - 1;
+}
+
+void i2c_select_port(int port)
+{
+	/*
+	 * I2C0_1 uses port 1 of controller 0. All other I2C pin sets
+	 * use port 0.
+	 */
+	if (port > NPCX_I2C_PORT0_1)
+		return;
+
+	/* Select IO pins for multi-ports I2C controllers */
+	UPDATE_BIT(NPCX_GLUE_SMBSEL, NPCX_SMBSEL_SMB0SEL,
+			(port == NPCX_I2C_PORT0_1));
+}
+
+int i2c_is_raw_mode(int port)
+{
+	int bit = (port > NPCX_I2C_PORT0_1) ? ((port - 1) * 2) : port;
+
+	if (IS_BIT_SET(NPCX_DEVALT(2), bit))
+		return 0;
+	else
+		return 1;
+}
+