diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-17 13:56:46 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-10-26 01:44:08 -0700 |
| commit | 5cfa02b03c2b90918fbbb238ab736758bd601281 (patch) | |
| tree | dc6e818d6d2f2e1518c7726059dfdaedc320669d /chip/npcx/lpc.c | |
| parent | b142b05465052511b837ac71ab079081ff9430ae (diff) | |
| download | chrome-ec-5cfa02b03c2b90918fbbb238ab736758bd601281.tar.gz | |
lpc: Add function for host reset without RCIN GPIO
Prior x86 boards have had GPIO for toggling RCIN directly on the PCH,
although many likely had HW-assisted methods as well.
With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality
software control over RCIN Virtual Wire is not available with the npcx EC,
so the legacy LPC interface for pulsing KBRST must be used instead as this
is the only way to generate RCIN.
This method will likely vary on different EC chips, but for skylake it
can just be abstracted into the LPC module.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=successful 'apreset warm' on eve EC console
Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400037
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/npcx/lpc.c')
| -rw-r--r-- | chip/npcx/lpc.c | 31 |
1 files changed, 29 insertions, 2 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 40ce230d9a..7c08062e1e 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -799,7 +799,34 @@ DECLARE_DEFERRED(lpc_chipset_reset); int lpc_get_pltrst_asserted(void) { /* Read current PLTRST status */ - return (NPCX_MSWCTL1 & 0x04) ? 1 : 0; + return IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_PLTRST_ACT); +} + +void lpc_host_reset(void) +{ + /* Host Reset Control will assert KBRST# (LPC) or RCIN# VW (eSPI) */ +#ifdef CONFIG_ESPI_VW_SIGNALS + int timeout = 100; /* 100 * 10us = 1ms */ + + /* Assert RCIN# VW to host */ + SET_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); + + /* Poll for dirty bit to clear to indicate VW read by host */ + while ((NPCX_VWEVSM(2) & VWEVSM_DIRTY(1))) { + if (!timeout--) { + CPRINTS("RCIN# VW Timeout"); + break; + } + udelay(10); + } + + /* Deassert RCIN# VW to host */ + CLEAR_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); +#else + SET_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); + udelay(10); + CLEAR_BIT(NPCX_MSWCTL1, NPCX_MSWCTL1_HRSTOB); +#endif } #ifndef CONFIG_ESPI @@ -855,7 +882,7 @@ static void lpc_init(void) NPCX_DEVCNT |= 0x04; #endif /* Enable 4E/4F */ - if (!IS_BIT_SET(NPCX_MSWCTL1, 3)) { + if (!IS_BIT_SET(NPCX_MSWCTL1, NPCX_MSWCTL1_VHCFGA)) { NPCX_HCBAL = 0x4E; NPCX_HCBAH = 0x0; } |