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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2016-11-02 11:04:47 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-20 22:40:32 -0800 |
| commit | 8e4d4291726831cc35b3991418331db9a247a98b (patch) | |
| tree | 817dcf27c29cc9946c2af92119302cecb0484667 /chip/npcx/lpc.c | |
| parent | 2b54aa9a9b061117021eff22385c9de474ab090b (diff) | |
| download | chrome-ec-8e4d4291726831cc35b3991418331db9a247a98b.tar.gz | |
power: Group Intel x86 power sequencing common code
Grouping the Intel x86 power sequencing common code so that
the future chipset power sequencing implementation can make
use of the existing code.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Manually tested on Reef & Chell.
System can boot to OS. S3, S5, hibernate are working.
Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/402272
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'chip/npcx/lpc.c')
0 files changed, 0 insertions, 0 deletions