diff options
| author | Scott Collyer <scollyer@google.com> | 2021-05-21 11:33:37 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-27 01:38:30 +0000 |
| commit | ebede7bc951cbaa75dc24bd66d8705ae62a6dab0 (patch) | |
| tree | 8b7305194cbedd640f5a4b4da9dc1f44934b9676 /chip/npcx/registers-npcx5.h | |
| parent | 2a85f58b5c17afc725784de5c9d86dcd3a1ba9d8 (diff) | |
| download | chrome-ec-ebede7bc951cbaa75dc24bd66d8705ae62a6dab0.tar.gz | |
stm32g4: flash: Add DBANK support to option bytes WRP
This CL adds support for the option bytes for dual-bank (DBANK)
mode in category 3 devices. The MCU being used on honeybuns,
is a category 3 flash device and DBANK mode is enalbed in the option
bytes by default.
When DBANK mode is enabled, then more than 1 WRP register is needed to
protect the RW image. In this mode, WRP register can only protect 64
flash pages in one flash bank.
BUG=b:183686750
BRANCH=quiche
TEST=
Case 1: HW WP active and code executing in RW
> flashinfo
Usable: 256 KB
Write: 4 B (ideal 4 B)
Erase: 2048 B (to 1-bits)
Protect: 2048 B
flash-phy: WRP_RO: start = 0, end = 31
flash-phy: WRP_RW: start = 32, end = 127
Flags: wp_gpio_asserted ro_at_boot ro_now all_now
Protected now:
YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY
YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY
YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY
YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY
Case 2: HW WP active active and code executing in RO
flashinfo
Usable: 256 KB
Write: 4 B (ideal 4 B)
Erase: 2048 B (to 1-bits)
Protect: 2048 B
flash-phy: WRP_RO: start = 0, end = 31
flash-phy: WRP_RW: start = 127, end = 0
Flags: wp_gpio_asserted ro_at_boot ro_now
Protected now:
YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY
........ ........ ........ ........
........ ........ ........ ........
........ ........ ........ ........
Case 3: HW WP disabled
> flashinfo
Usable: 256 KB
Write: 4 B (ideal 4 B)
Erase: 2048 B (to 1-bits)
Protect: 2048 B
flash-phy: WRP_RO: start = 127, end = 0
flash-phy: WRP_RW: start = 127, end = 0
Flags: ro_at_boot
Protected now:
........ ........ ........ ........
........ ........ ........ ........
........ ........ ........ ........
........ ........ ........ ........
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I72c03029b0231ee864afc967905c50acba4ba5de
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911738
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'chip/npcx/registers-npcx5.h')
0 files changed, 0 insertions, 0 deletions