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| author | Jun Lin <CHLin56@nuvoton.com> | 2021-04-27 16:12:11 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-04-29 03:03:47 +0000 |
| commit | 24be106a07765b0c5416fa8fdb3e976e40dbaf5e (patch) | |
| tree | 69c574a7edac3803feb7de911269d6f75e0264cb /chip/npcx/registers.h | |
| parent | 8bc05328420e50ecf17c41e237eb4210a43eef46 (diff) | |
| download | chrome-ec-24be106a07765b0c5416fa8fdb3e976e40dbaf5e.tar.gz | |
npcx9: port80: support 4 bytes mode for eSPI host interface
eSPI PUT_IOWR_SHORT protocol can send a max of 4 bytes of data in a
single transaction. This allows the host to send 4 bytes of the Port80
code at one time. This CL sets the bit OFS0_SEL~OFS3_SEL in the DPAR1
register to let the EC hardware put full 4-bytes of Port80 code to
DP80BUF FIFO. It also groups the 4-byte code into a single 32-bits
variable when necessary by analyzing the offset field in the DP80BUF
register.
BRANCH=none
BUG=b:184872297
TEST=build the image with "#define CONFIG_PORT80_PRINT_IN_INT 1";
connect npcx9_evb to the eSPI host emulator; the host sends a
PUT_IOWR_SHORT transaction to IO address 0x80 with 4 bytes of code
"0xEEE20400"; the EC console shows:
[63.694685 Port 80: 0xeee20400]
Then the host sends a single byte "0xaa" to Port80, the EC console
prints:
[576.531790 Port 80: 0xaa]
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I5dfbc0d08172042cb43d72eeb6f0e7da63feccf0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847668
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'chip/npcx/registers.h')
| -rw-r--r-- | chip/npcx/registers.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 3fc3fbe1e9..aaf7f0477e 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -794,6 +794,7 @@ enum { #define NPCX_PWIN_SIZEI_WPROT 14 #define NPCX_CSEM2 6 #define NPCX_CSEM3 7 +#define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3) #define NPCX_DP80STS_FWR 5 #define NPCX_DP80STS_FNE 6 #define NPCX_DP80STS_FOR 7 |