diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-05-24 17:51:42 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-06-09 21:44:06 -0700 |
| commit | a08d004e97e3bd6fe232b5f050bad2c448f381c0 (patch) | |
| tree | df87cceb5389560e70bde1c68f60b95e8e433548 /chip/npcx/registers.h | |
| parent | e9215ba711d337e4cfc9524c4ef07b03a813c8fb (diff) | |
| download | chrome-ec-a08d004e97e3bd6fe232b5f050bad2c448f381c0.tar.gz | |
npcx: clock: Add support for external 32kHz crystal osc.
In this CL, we add selecting LFCLK sources functionality for npcx7 ec
series. (Please notice not all of npcx7 ec series support this feature.)
Beside internal LFCLK source, ec also can choose the external 32kHz
crystal oscillator as LFCLK source for the specific application. We also
introduce a new definition, CONFIG_CLOCK_SRC_EXTERNAL, to switch this
feature in the board level driver.
This CL also adds:
1. LFCG register definitions in registers.h.
2. Change the order of each npcx modules by memory address.
BRANCH=none
BUG=none
TEST=Output LFCLK source through GPIO75. Compare with external 32kHz
crystal osc. on npcx7_evb and make sure the sources are the same.
Change-Id: I137146bf51ccb51266b9aac1e2e28bcea87dc4f5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/520745
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/registers.h')
| -rw-r--r-- | chip/npcx/registers.h | 23 |
1 files changed, 19 insertions, 4 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index e07870cfc2..979833d5b0 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -65,16 +65,19 @@ #define DEBUG_ESPI 0 /* Modules Map */ +#define NPCX_ESPI_BASE_ADDR 0x4000A000 #define NPCX_MDC_BASE_ADDR 0x4000C000 -#define NPCX_SIB_BASE_ADDR 0x4000E000 #define NPCX_PMC_BASE_ADDR 0x4000D000 +#define NPCX_SIB_BASE_ADDR 0x4000E000 +#define NPCX_SHI_BASE_ADDR 0x4000F000 #define NPCX_SHM_BASE_ADDR 0x40010000 +#define NPCX_GDMA_BASE_ADDR 0x40011000 #define NPCX_FIU_BASE_ADDR 0x40020000 #define NPCX_KBSCAN_REGS_BASE 0x400A3000 #define NPCX_GLUE_REGS_BASE 0x400A5000 #define NPCX_BBRAM_BASE_ADDR 0x400AF000 #define NPCX_HFCG_BASE_ADDR 0x400B5000 -#define NPCX_SHI_BASE_ADDR 0x4000F000 +#define NPCX_LFCG_BASE_ADDR 0x400B5100 #define NPCX_MTC_BASE_ADDR 0x400B7000 #define NPCX_MSWC_BASE_ADDR 0x400C1000 #define NPCX_SCFG_BASE_ADDR 0x400C3000 @@ -84,8 +87,6 @@ #define NPCX_SPI_BASE_ADDR 0x400D2000 #define NPCX_PECI_BASE_ADDR 0x400D4000 #define NPCX_TWD_BASE_ADDR 0x400D8000 -#define NPCX_ESPI_BASE_ADDR 0x4000A000 -#define NPCX_GDMA_BASE_ADDR 0x40011000 /* Multi-Modules Map */ #define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) @@ -271,6 +272,20 @@ #define NPCX_HFCGCTRL_CLK_CHNG 7 /******************************************************************************/ +/* Low Frequency Clock Generator (LFCG) registers */ +#define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000) +#define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002) +#define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004) +#define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006) +#define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008) +#define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A) +#define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014) + +/* LFCG register fields */ +#define NPCX_LFCGCTL_XTCLK_VAL 7 +#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6 + +/******************************************************************************/ /*CR UART Register */ #define NPCX_UTBUF REG8(NPCX_CR_UART_BASE_ADDR + 0x000) #define NPCX_URBUF REG8(NPCX_CR_UART_BASE_ADDR + 0x002) |