diff options
author | CHLin <CHLin56@nuvoton.com> | 2020-09-07 15:45:33 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-09-22 04:49:55 +0000 |
commit | 1ba3b3d64b0cc58c107a5d24079999deea0bb03b (patch) | |
tree | d5b7886e969655bb7c3b27b25f11d9e18b7109a6 /chip/npcx/registers.h | |
parent | d03abea4c36062f922182b95e046fc6817e98eec (diff) | |
download | chrome-ec-1ba3b3d64b0cc58c107a5d24079999deea0bb03b.tar.gz |
npcx: change registers and hwtimer to support npcx9
This CL makes the following changes to support npcx9.
1. Split the CHIP_FAMILY specific register setting form register.h to
register-npcx5.h and register-npcx7.h.
2. Add npcx9's specific register setting in registers-npcx9.h
3. In npcx9, all 16-bit timers are removed from ITIM module. Change
the hwtimer driver to use 32-bit timer for npcx9.
The table shows the supported and current use of ITIM modules in the
system:
NPCX5/7 NPCX9
Change-Id: I1d00cbb8d36bff37563cfeaf78e338286e779b00
-------------------|---------------------|--------------------|
Supported ITIMs | ITIM16_1-ITIM16_6 | ITIM32_1-ITIM32_6 |
| ITIM32 | |
-------------------|---------------------|--------------------|
System tick timer | ITIM32 | ITIM32_6 |
-------------------|---------------------|--------------------|
Event timer | ITIM16_1 | ITIM32_1 |
-------------------|---------------------|--------------------|
Watchdog timer | ITIM16_5 | ITIM32_5 |
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=boot up EC on the npcx7/npcx9 EVB. Check HOOT_SECOND function is
working; EC watchdog resets after console command "waitms 4000"
TEST=build and flash image for yorp, no symptom occurred.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ibf0fa5fa44590de6bb3e1bff677f40aafd70b556
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402840
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'chip/npcx/registers.h')
-rw-r--r-- | chip/npcx/registers.h | 649 |
1 files changed, 16 insertions, 633 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 8ed003ab5c..403d40b4a3 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -19,7 +19,7 @@ /* Bit functions */ #define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) #define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) -#define IS_BIT_SET(reg, bit) ((reg >> bit) & (0x1)) +#define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) #define UPDATE_BIT(reg, bit, cond) { if (cond) \ SET_BIT(reg, bit); \ else \ @@ -99,25 +99,10 @@ /* Multi-Modules Map */ #define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) #define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl) * 0x2000L)) -#define NPCX_ITIM16_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) -#define NPCX_ITIM32_BASE_ADDR 0x400BC000 +#define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) #define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl) * 0x2000L)) #define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl) * 0x2000L)) -#define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) #define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl) * 0x2000L)) -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - ((mdl) < 4) ? \ - (0x400C0000 + (((mdl) - 2) * 0x2000L)) : \ - ((mdl) == 4) ? \ - (0x40008000) : \ - (0x40017000 + (((mdl) - 5) * 0x1000L))) -#else -#define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ - (0x40009000 + ((mdl) * 0x2000L)) : \ - (0x400C0000 + (((mdl) - 2) * 0x2000L))) -#endif /* * NPCX-IRQ numbers @@ -187,72 +172,6 @@ #define NPCX_IRQ_62 62 #define NPCX_IRQ_63 63 -#define NPCX_IRQ0_NOUSED NPCX_IRQ_0 -#define NPCX_IRQ1_NOUSED NPCX_IRQ_1 -#define NPCX_IRQ_KBSCAN NPCX_IRQ_2 -#define NPCX_IRQ_PM_CHAN_OBE NPCX_IRQ_3 -#define NPCX_IRQ_PECI NPCX_IRQ_4 -#define NPCX_IRQ5_NOUSED NPCX_IRQ_5 -#define NPCX_IRQ_PORT80 NPCX_IRQ_6 -#define NPCX_IRQ_MTC_WKINTAD_0 NPCX_IRQ_7 -#define NPCX_IRQ_SMB8 NPCX_IRQ_8 -#define NPCX_IRQ_MFT_1 NPCX_IRQ_9 -#define NPCX_IRQ_ADC NPCX_IRQ_10 -#define NPCX_IRQ_WKINTEFGH_0 NPCX_IRQ_11 -#define NPCX_IRQ_CDMA NPCX_IRQ_12 -#define NPCX_IRQ_SMB1 NPCX_IRQ_13 -#define NPCX_IRQ_SMB2 NPCX_IRQ_14 -#define NPCX_IRQ_WKINTC_0 NPCX_IRQ_15 -#define NPCX_IRQ_SMB7 NPCX_IRQ_16 -#define NPCX_IRQ_ITIM16_3 NPCX_IRQ_17 -#define NPCX_IRQ_SHI NPCX_IRQ_18 -#define NPCX_IRQ_ESPI NPCX_IRQ_18 -#define NPCX_IRQ_SMB5 NPCX_IRQ_19 -#define NPCX_IRQ_SMB6 NPCX_IRQ_20 -#define NPCX_IRQ_PS2 NPCX_IRQ_21 -#define NPCX_IRQ_WOV NPCX_IRQ_22 -#define NPCX_IRQ_MFT_2 NPCX_IRQ_23 -#define NPCX_IRQ_SHM NPCX_IRQ_24 -#define NPCX_IRQ_KBC_IBF NPCX_IRQ_25 -#define NPCX_IRQ_PM_CHAN_IBF NPCX_IRQ_26 -#define NPCX_IRQ_ITIM16_2 NPCX_IRQ_27 -#define NPCX_IRQ_ITIM16_1 NPCX_IRQ_28 -#define NPCX_IRQ29_NOUSED NPCX_IRQ_29 -#define NPCX_IRQ30_NOUSED NPCX_IRQ_30 -#define NPCX_IRQ_TWD_WKINTB_0 NPCX_IRQ_31 -#define NPCX_IRQ_UART2 NPCX_IRQ_32 -#define NPCX_IRQ_UART NPCX_IRQ_33 -#define NPCX_IRQ34_NOUSED NPCX_IRQ_34 -#define NPCX_IRQ35_NOUSED NPCX_IRQ_35 -#define NPCX_IRQ_SMB3 NPCX_IRQ_36 -#define NPCX_IRQ_SMB4 NPCX_IRQ_37 -#define NPCX_IRQ38_NOUSED NPCX_IRQ_38 -#define NPCX_IRQ39_NOUSED NPCX_IRQ_39 -#define NPCX_IRQ40_NOUSED NPCX_IRQ_40 -#define NPCX_IRQ_MFT_3 NPCX_IRQ_41 -#define NPCX_IRQ42_NOUSED NPCX_IRQ_42 -#define NPCX_IRQ_ITIM16_4 NPCX_IRQ_43 -#define NPCX_IRQ_ITIM16_5 NPCX_IRQ_44 -#define NPCX_IRQ_ITIM16_6 NPCX_IRQ_45 -#define NPCX_IRQ_ITIM32 NPCX_IRQ_46 -#define NPCX_IRQ_WKINTA_1 NPCX_IRQ_47 -#define NPCX_IRQ_WKINTB_1 NPCX_IRQ_48 -#define NPCX_IRQ_KSI_WKINTC_1 NPCX_IRQ_49 -#define NPCX_IRQ_WKINTD_1 NPCX_IRQ_50 -#define NPCX_IRQ_WKINTE_1 NPCX_IRQ_51 -#define NPCX_IRQ_WKINTF_1 NPCX_IRQ_52 -#define NPCX_IRQ_WKINTG_1 NPCX_IRQ_53 -#define NPCX_IRQ_WKINTH_1 NPCX_IRQ_54 -#define NPCX_IRQ55_NOUSED NPCX_IRQ_55 -#define NPCX_IRQ_KBC_OBE NPCX_IRQ_56 -#define NPCX_IRQ_SPI NPCX_IRQ_57 -#define NPCX_IRQ58_NOUSED NPCX_IRQ_58 -#define NPCX_IRQ_WKINTFG_2 NPCX_IRQ_59 -#define NPCX_IRQ_WKINTA_2 NPCX_IRQ_60 -#define NPCX_IRQ_WKINTB_2 NPCX_IRQ_61 -#define NPCX_IRQ_WKINTC_2 NPCX_IRQ_62 -#define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 - #define NPCX_IRQ_COUNT 64 /******************************************************************************/ @@ -271,10 +190,6 @@ #define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006) #define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008) #define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010) -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_HFCBCD1 REG8(NPCX_HFCG_BASE_ADDR + 0x012) -#define NPCX_HFCBCD2 REG8(NPCX_HFCG_BASE_ADDR + 0x014) -#endif /* HFCG register fields */ #define NPCX_HFCGCTRL_LOAD 0 @@ -305,53 +220,6 @@ #define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A) #define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C) #define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E) -#ifdef NPCX_UART_FIFO_SUPPORT - /* UART registers only used for FIFO mode */ -#define NPCX_UFTSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x020) -#define NPCX_UFRSTS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x022) -#define NPCX_UFTCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x024) -#define NPCX_UFRCTL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x026) - -/* UART FIFO register fields */ -#define NPCX_UMDSL_FIFO_MD 0 - -#define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5) -#define NPCX_UFTSTS_TEMPTY_LVL_STS 5 -#define NPCX_UFTSTS_TFIFO_EMPTY_STS 6 -#define NPCX_UFTSTS_NXMIP 7 - -#define NPCX_UFRSTS_RFULL_LVL_STS 5 -#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6 -#define NPCX_UFRSTS_ERR 7 - -#define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5) -#define NPCX_UFTCTL_TEMPTY_LVL_EN 5 -#define NPCX_UFTCTL_TEMPTY_EN 6 -#define NPCX_UFTCTL_NXMIPEN 7 - -#define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5) -#define NPCX_UFRCTL_RFULL_LVL_EN 5 -#define NPCX_UFRCTL_RNEMPTY_EN 6 -#define NPCX_UFRCTL_ERR_EN 7 - -#endif - -#if defined(CHIP_FAMILY_NPCX5) -enum { - NPCX_UART_PORT0 = 0, /* UART port 0 */ - NPCX_UART_COUNT -}; -#elif defined(CHIP_FAMILY_NPCX7) -enum { - NPCX_UART_PORT0 = 0, /* UART port 0 */ -#ifdef NPCX_SECOND_UART - NPCX_UART_PORT1 = 1, /* UART port 1 */ -#endif - NPCX_UART_COUNT -}; -#else -#error "Unsupported chip family for uart ports." -#endif /******************************************************************************/ /* KBSCAN registers */ @@ -374,9 +242,6 @@ enum { #define NPCX_KBSMODE 1 #define NPCX_KBSIEN 2 #define NPCX_KBSINC 3 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_KBHDRV_FIELD FIELD(6, 2) -#endif #define NPCX_KBSCFGINDX 0 /* KBSCAN definitions */ @@ -390,32 +255,7 @@ enum { #define NPCX_GLUE_SDPD1 REG8(NPCX_GLUE_REGS_BASE + 0x012) #define NPCX_GLUE_SDP_CTS REG8(NPCX_GLUE_REGS_BASE + 0x014) #define NPCX_GLUE_SMBSEL REG8(NPCX_GLUE_REGS_BASE + 0x021) -#if defined(NPCX_PSL_MODE_SUPPORT) -#define NPCX_GLUE_PSL_CTS REG8(NPCX_GLUE_REGS_BASE + 0x027) -#endif /******************************************************************************/ -/* MIWU registers */ -#define NPCX_WKEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x00 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKAEDG_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x01 + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x1E)) -#define NPCX_WKPND_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0A + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKPCL_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x0C + \ - ((n) * 4L) + ((n) < 5 ? 0 : 0x10)) -#define NPCX_WKEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1E + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKINEN_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x1F + \ - ((n) * 2L) + ((n) < 5 ? 0 : 0x12)) -#define NPCX_WKMOD_ADDR(port, n) (NPCX_MIWU_BASE_ADDR(port) + 0x70 + (n)) - -#define NPCX_WKEDG(port, n) REG8(NPCX_WKEDG_ADDR(port, n)) -#define NPCX_WKAEDG(port, n) REG8(NPCX_WKAEDG_ADDR(port, n)) -#define NPCX_WKPND(port, n) REG8(NPCX_WKPND_ADDR(port, n)) -#define NPCX_WKPCL(port, n) REG8(NPCX_WKPCL_ADDR(port, n)) -#define NPCX_WKEN(port, n) REG8(NPCX_WKEN_ADDR(port, n)) -#define NPCX_WKINEN(port, n) REG8(NPCX_WKINEN_ADDR(port, n)) -#define NPCX_WKMOD(port, n) REG8(NPCX_WKMOD_ADDR(port, n)) /* MIWU enumeration */ enum { @@ -456,9 +296,6 @@ enum { #define NPCX_PPUD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x004) #define NPCX_PENVDD(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x005) #define NPCX_PTYPE(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x006) -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_PLOCK_CTL(n) REG8(NPCX_GPIO_BASE_ADDR(n) + 0x007) -#endif /* GPIO enumeration */ enum { @@ -536,45 +373,15 @@ enum { #define NPCX_STRPST REG8(NPCX_SCFG_BASE_ADDR + 0x001) #define NPCX_RSTCTL REG8(NPCX_SCFG_BASE_ADDR + 0x002) #define NPCX_DEV_CTL4 REG8(NPCX_SCFG_BASE_ADDR + 0x006) -#define NPCX_DEVALT(n) REG8(NPCX_SCFG_BASE_ADDR + 0x010 + (n)) #define NPCX_LFCGCALCNT REG8(NPCX_SCFG_BASE_ADDR + 0x021) #define NPCX_PUPD_EN0 REG8(NPCX_SCFG_BASE_ADDR + 0x028) #define NPCX_PUPD_EN1 REG8(NPCX_SCFG_BASE_ADDR + 0x029) -#if defined(CHIP_FAMILY_NPCX5) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_SCFG_BASE_ADDR + 0x02A + (n)) -#elif defined(CHIP_FAMILY_NPCX7) -#define NPCX_LV_GPIO_CTL_ADDR(n) (((n) < 5) ? \ - (NPCX_SCFG_BASE_ADDR + 0x02A + (n)) :\ - (NPCX_SCFG_BASE_ADDR + 0x026)) -#define NPCX_LV_GPIO_CTL(n) REG8(NPCX_LV_GPIO_CTL_ADDR(n)) -#endif #define NPCX_SCFG_VER REG8(NPCX_SCFG_BASE_ADDR + 0x02F) #define TEST_BKSL REG8(NPCX_SCFG_BASE_ADDR + 0x037) #define TEST0 REG8(NPCX_SCFG_BASE_ADDR + 0x038) #define BLKSEL 0 -/* SCFG enumeration */ -enum { - ALT_GROUP_0, - ALT_GROUP_1, - ALT_GROUP_2, - ALT_GROUP_3, - ALT_GROUP_4, - ALT_GROUP_5, - ALT_GROUP_6, - ALT_GROUP_7, - ALT_GROUP_8, - ALT_GROUP_9, - ALT_GROUP_A, - ALT_GROUP_B, - ALT_GROUP_C, - ALT_GROUP_D, - ALT_GROUP_E, - ALT_GROUP_F, - ALT_GROUP_COUNT -}; - /* SCFG register fields */ #define NPCX_DEVCNT_F_SPI_TRIS 6 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2) @@ -620,27 +427,6 @@ enum { #define NPCX_DEVALT1_CLKRN_SL 6 #define NPCX_DEVALT1_NO_LPC_ESPI 7 -/* pin-mux for I2C */ -#if defined(CHIP_FAMILY_NPCX5) -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C0_1_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C3_0_SL 6 -#elif defined(CHIP_FAMILY_NPCX7) -#define NPCX_DEVALT2_I2C0_0_SL 0 -#define NPCX_DEVALT2_I2C7_0_SL 1 -#define NPCX_DEVALT2_I2C1_0_SL 2 -#define NPCX_DEVALT2_I2C6_0_SL 3 -#define NPCX_DEVALT2_I2C2_0_SL 4 -#define NPCX_DEVALT2_I2C5_0_SL 5 -#define NPCX_DEVALT2_I2C3_0_SL 6 -#define NPCX_DEVALT2_I2C4_0_SL 7 -#define NPCX_DEVALT6_I2C6_1_SL 5 -#define NPCX_DEVALT6_I2C5_1_SL 6 -#define NPCX_DEVALT6_I2C4_1_SL 7 -#endif - /* pin-mux for PS2 */ #define NPCX_DEVALT3_PS2_0_SL 0 #define NPCX_DEVALT3_PS2_1_SL 1 @@ -679,13 +465,6 @@ enum { #define NPCX_DEVALT6_ADC2_SL 2 #define NPCX_DEVALT6_ADC3_SL 3 #define NPCX_DEVALT6_ADC4_SL 4 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_DEVALTF_ADC5_SL 0 -#define NPCX_DEVALTF_ADC6_SL 1 -#define NPCX_DEVALTF_ADC7_SL 2 -#define NPCX_DEVALTF_ADC8_SL 3 -#define NPCX_DEVALTF_ADC9_SL 4 -#endif /* pin-mux for Keyboard */ #define NPCX_DEVALT7_NO_KSI0_SL 0 @@ -715,44 +494,12 @@ enum { #define NPCX_DEVALTA_NO_KSO16_SL 0 #define NPCX_DEVALTA_NO_KSO17_SL 1 -/* pin-mux for PSL */ -#if defined(NPCX_PSL_MODE_SUPPORT) -#define NPCX_DEVALTD_PSL_IN1_AHI 0 -#define NPCX_DEVALTD_NPSL_IN1_SL 1 -#define NPCX_DEVALTD_PSL_IN2_AHI 2 -#define NPCX_DEVALTD_NPSL_IN2_SL 3 -#define NPCX_DEVALTD_PSL_IN3_AHI 4 -#define NPCX_DEVALTD_PSL_IN3_SL 5 -#define NPCX_DEVALTD_PSL_IN4_AHI 6 -#define NPCX_DEVALTD_PSL_IN4_SL 7 -#endif - /* pin-mux for Others */ #define NPCX_DEVALTA_32K_OUT_SL 2 -#if !defined(NPCX_EXT32K_OSC_SUPPORT) -#define NPCX_DEVALTA_32KCLKIN_SL 3 -#endif #define NPCX_DEVALTA_NO_VCC1_RST 4 -#ifdef NPCX_SECOND_UART -#define NPCX_DEVALTA_UART2_SL 5 -#endif #define NPCX_DEVALTA_NO_PECI_EN 6 -#define NPCX_DEVALTA_UART_SL1 7 -#define NPCX_DEVALTC_UART_SL2 0 #define NPCX_DEVALTC_SHI_SL 1 -#if defined(CHIP_FAMILY_NPCX7) -/* SHI module version 2 enable bit */ -#define NPCX_DEVALTF_SHI_NEW 7 -#endif - -/* pin-mux for WoV */ -#ifdef NPCX_WOV_SUPPORT -#define NPCX_DEVALTE_WOV_SL 0 -#define NPCX_DEVALTE_I2S_SL 1 -#define NPCX_DEVALTE_DMCLK_FAST 2 -#endif - /* Others bit definitions */ #define NPCX_LFCGCALCNT_LPREG_CTL_EN 1 @@ -857,13 +604,6 @@ enum { #define NPCX_SMBADDR6_SAEN 7 #define NPCX_SMBADDR7_SAEN 7 #define NPCX_SMBADDR8_SAEN 7 -#if defined(CHIP_FAMILY_NPCX5) -#define NPCX_SMBSEL_SMB0SEL 0 -#elif defined(CHIP_FAMILY_NPCX7) -#define NPCX_SMBSEL_SMB4SEL 4 -#define NPCX_SMBSEL_SMB5SEL 5 -#define NPCX_SMBSEL_SMB6SEL 6 -#endif #define NPCX_SMBFIF_CTS_RXF_TXE 1 #define NPCX_SMBFIF_CTS_CLR_FIFO 6 @@ -877,39 +617,6 @@ enum { * In master receiving mode, last byte in FIFO should send ACK or NACK */ #define NPCX_SMBRXF_CTL_LAST 7 -/* - * SMB enumeration - * I2C port definitions. - */ -#if defined(CHIP_FAMILY_NPCX5) -enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT0_1, /* I2C port 0, bus 1 */ - NPCX_I2C_PORT1, /* I2C port 1 */ - NPCX_I2C_PORT2, /* I2C port 2 */ - NPCX_I2C_PORT3, /* I2C port 3 */ - NPCX_I2C_COUNT, -}; -#elif defined(CHIP_FAMILY_NPCX7) -enum { - NPCX_I2C_PORT0_0 = 0, /* I2C port 0, bus 0 */ - NPCX_I2C_PORT1_0, /* I2C port 1, bus 0 */ - NPCX_I2C_PORT2_0, /* I2C port 2, bus 0 */ - NPCX_I2C_PORT3_0, /* I2C port 3, bus 0 */ -#if !defined(NPCX_PSL_MODE_SUPPORT) - NPCX_I2C_PORT4_0, /* I2C port 4, bus 0 */ -#endif - NPCX_I2C_PORT4_1, /* I2C port 4, bus 1 */ - NPCX_I2C_PORT5_0, /* I2C port 5, bus 0 */ - NPCX_I2C_PORT5_1, /* I2C port 5, bus 1 */ - NPCX_I2C_PORT6_0, /* I2C port 6, bus 0 */ - NPCX_I2C_PORT6_1, /* I2C port 6, bus 1 */ - NPCX_I2C_PORT7_0, /* I2C port 7, bus 0 */ - NPCX_I2C_COUNT, -}; -#else -#error "Unsupported chip family for i2c ports." -#endif /******************************************************************************/ /* Power Management Controller (PMC) Registers */ @@ -921,10 +628,6 @@ enum { (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \ (NPCX_PMC_BASE_ADDR + 0x024)) #define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) -#define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + offset) -#endif /* PMC register fields */ #define NPCX_PMCSR_DI_INSTW 0 @@ -958,9 +661,6 @@ enum { #define NPCX_PWDWN_CTL3_SMB1_PD 1 #define NPCX_PWDWN_CTL3_SMB2_PD 2 #define NPCX_PWDWN_CTL3_SMB3_PD 3 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_PWDWN_CTL3_SMB4_PD 4 -#endif #define NPCX_PWDWN_CTL3_GMDA_PD 7 #define NPCX_PWDWN_CTL4_ITIM1_PD 0 #define NPCX_PWDWN_CTL4_ITIM2_PD 1 @@ -980,62 +680,6 @@ enum { #define NPCX_PWDWN_CTL6_ITIM5_PD 1 #define NPCX_PWDWN_CTL6_ITIM6_PD 2 #define NPCX_PWDWN_CTL6_ESPI_PD 7 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_PWDWN_CTL7_SMB5_PD 0 -#define NPCX_PWDWN_CTL7_SMB6_PD 1 -#define NPCX_PWDWN_CTL7_SMB7_PD 2 -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ - defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ - defined(CHIP_VARIANT_NPCX7M7WC) -#define NPCX_PWDWN_CTL7_ITIM64_PD 5 -#define NPCX_PWDWN_CTL7_UART2_PD 6 -#endif -#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC) -#define NPCX_PWDWN_CTL7_WOV_PD 7 -#endif -#endif - -/* - * PMC enumeration - * Offsets from CGC_BASE registers for each peripheral. - */ -enum { - CGC_OFFSET_KBS = 0, - CGC_OFFSET_UART = 0, - CGC_OFFSET_FAN = 0, - CGC_OFFSET_FIU = 0, - CGC_OFFSET_PS2 = 0, - CGC_OFFSET_PWM = 1, - CGC_OFFSET_I2C = 2, - CGC_OFFSET_ADC = 3, - CGC_OFFSET_PECI = 3, - CGC_OFFSET_SPI = 3, - CGC_OFFSET_TIMER = 3, - CGC_OFFSET_LPC = 4, - CGC_OFFSET_ESPI = 5, -#if defined(CHIP_FAMILY_NPCX7) - CGC_OFFSET_I2C2 = 6, -#ifdef NPCX_SECOND_UART - CGC_OFFSET_UART2 = 6, -#endif -#ifdef NPCX_WOV_SUPPORT - CGC_OFFSET_WOV = 6, -#endif -#endif -}; - -enum NPCX_PMC_PWDWN_CTL_T { - NPCX_PMC_PWDWN_1 = 0, - NPCX_PMC_PWDWN_2 = 1, - NPCX_PMC_PWDWN_3 = 2, - NPCX_PMC_PWDWN_4 = 3, - NPCX_PMC_PWDWN_5 = 4, - NPCX_PMC_PWDWN_6 = 5, -#if defined(CHIP_FAMILY_NPCX7) - NPCX_PMC_PWDWN_7 = 6, -#endif - NPCX_PMC_PWDWN_CNT, -}; /* TODO: set PD masks based upon actual peripheral usage */ #define CGC_KBS_MASK BIT(NPCX_PWDWN_CTL1_KBS_PD) @@ -1044,27 +688,6 @@ enum NPCX_PMC_PWDWN_CTL_T { BIT(NPCX_PWDWN_CTL1_MFT2_PD)) #define CGC_FIU_MASK BIT(NPCX_PWDWN_CTL1_FIU_PD) #define CGC_PS2_MASK BIT(NPCX_PWDWN_CTL1_PS2_PD) -#if defined(CHIP_FAMILY_NPCX5) -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD)) -#elif defined(CHIP_FAMILY_NPCX7) -#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ - BIT(NPCX_PWDWN_CTL3_SMB4_PD)) -#define CGC_I2C_MASK2 (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ - BIT(NPCX_PWDWN_CTL7_SMB7_PD)) -#ifdef NPCX_SECOND_UART -#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) -#endif -#ifdef NPCX_WOV_SUPPORT -#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD) -#endif -#endif #define CGC_ADC_MASK BIT(NPCX_PWDWN_CTL4_ADC_PD) #define CGC_PECI_MASK BIT(NPCX_PWDWN_CTL4_PECI_PD) #define CGC_SPI_MASK BIT(NPCX_PWDWN_CTL4_SPIP_PD) @@ -1271,19 +894,6 @@ enum PM_CHANNEL_T { /* BBRAM register fields */ #define NPCX_BKUP_STS_IBBR 7 -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ - defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ - defined(CHIP_VARIANT_NPCX7M7WC) -#define NPCX_BKUP_STS_VSBY_STS 1 -#define NPCX_BKUP_STS_VCC1_STS 0 -#define NPCX_BKUP_STS_ALL_MASK \ - (BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \ - BIT(NPCX_BKUP_STS_VCC1_STS)) -#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ -#else -#define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR) -#define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ -#endif /******************************************************************************/ /* Timer Watch Dog (TWD) Registers */ @@ -1314,56 +924,6 @@ enum PM_CHANNEL_T { #define NPCX_T0CSR_TESDIS 7 /******************************************************************************/ -/* ADC Registers */ -#define NPCX_ADCSTS REG16(NPCX_ADC_BASE_ADDR + 0x000) -#define NPCX_ADCCNF REG16(NPCX_ADC_BASE_ADDR + 0x002) -#define NPCX_ATCTL REG16(NPCX_ADC_BASE_ADDR + 0x004) -#define NPCX_ASCADD REG16(NPCX_ADC_BASE_ADDR + 0x006) -#define NPCX_ADCCS REG16(NPCX_ADC_BASE_ADDR + 0x008) -/* NOTE: These are 1-based for the threshold detectors. */ -#define NPCX_THRCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x012 + (2L*(n))) -#define NPCX_THRCTS REG16(NPCX_ADC_BASE_ADDR + 0x01A) -#define NPCX_THR_DCTL(n) REG16(NPCX_ADC_BASE_ADDR + 0x038 + (2L*(n))) -/* NOTE: This is 0-based for the ADC channels. */ -#define NPCX_CHNDAT(n) REG16(NPCX_ADC_BASE_ADDR + 0x040 + (2L*(n))) -#define NPCX_ADCCNF2 REG16(NPCX_ADC_BASE_ADDR + 0x020) -#define NPCX_GENDLY REG16(NPCX_ADC_BASE_ADDR + 0x022) -#define NPCX_MEAST REG16(NPCX_ADC_BASE_ADDR + 0x026) - -/* ADC register fields */ -#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6) -#define NPCX_ATCTL_DLY_FIELD FIELD(8, 3) -#define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5) -#define NPCX_ADCSTS_EOCEV 0 -#define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2) -#define NPCX_ADCCNF_ADCRPTC 3 -#define NPCX_ADCCNF_INTECEN 6 -#define NPCX_ADCCNF_START 4 -#define NPCX_ADCCNF_ADCEN 0 -#define NPCX_ADCCNF_STOP 11 -#define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10) -#define NPCX_CHNDAT_NEW 15 -#define NPCX_THRCTL_THEN 15 -#define NPCX_THRCTL_L_H 14 -#define NPCX_THRCTL_CHNSEL FIELD(10, 4) -#define NPCX_THRCTL_THRVAL FIELD(0, 10) -#define NPCX_THRCTS_ADC_WKEN 15 -#define NPCX_THRCTS_THR3_IEN 10 -#define NPCX_THRCTS_THR2_IEN 9 -#define NPCX_THRCTS_THR1_IEN 8 -#define NPCX_THRCTS_ADC_EVENT 7 -#define NPCX_THRCTS_THR3_STS 2 -#define NPCX_THRCTS_THR2_STS 1 -#define NPCX_THRCTS_THR1_STS 0 -#define NPCX_THR_DCTL_THRD_EN 15 -#define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10) - -#define NPCX_ADC_THRESH1 1 -#define NPCX_ADC_THRESH2 2 -#define NPCX_ADC_THRESH3 3 -#define NPCX_ADC_THRESH_CNT 3 - -/******************************************************************************/ /* SPI Register */ #define NPCX_SPI_DATA REG16(NPCX_SPI_BASE_ADDR + 0x00) #define NPCX_SPI_CTL1 REG16(NPCX_SPI_BASE_ADDR + 0x02) @@ -1468,16 +1028,11 @@ enum PM_CHANNEL_T { #define NPCX_TWUEN_TDWEN 3 /******************************************************************************/ /* ITIM16/32 Define */ -#define ITIM16_INT(module) CONCAT2(NPCX_IRQ_, module) +#define ITIM_INT(module) CONCAT2(NPCX_IRQ_, module) -/* ITIM16 registers */ -#define NPCX_ITCNT(n) REG8(NPCX_ITIM16_BASE_ADDR(n) + 0x000) -#define NPCX_ITPRE(n) REG8(NPCX_ITIM16_BASE_ADDR(n) + 0x001) -#define NPCX_ITCNT16(n) REG16(NPCX_ITIM16_BASE_ADDR(n) + 0x002) -#define NPCX_ITCTS(n) REG8(NPCX_ITIM16_BASE_ADDR(n) + 0x004) - -/* ITIM32 registers */ -#define NPCX_ITCNT32 REG32(NPCX_ITIM32_BASE_ADDR + 0x008) +/* ITIM16/32 register */ +#define NPCX_ITPRE(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x001) +#define NPCX_ITCTS(n) REG8(NPCX_ITIM_BASE_ADDR(n) + 0x004) /* ITIM16 register fields */ #define NPCX_ITCTS_TO_STS 0 @@ -1486,18 +1041,6 @@ enum PM_CHANNEL_T { #define NPCX_ITCTS_CKSEL 4 #define NPCX_ITCTS_ITEN 7 -/* ITIM16 enumeration*/ -enum ITIM16_MODULE_T { - ITIM16_1, - ITIM16_2, - ITIM16_3, - ITIM16_4, - ITIM16_5, - ITIM16_6, - ITIM32, - ITIM_MODULE_COUNT, -}; - /******************************************************************************/ /* Serial Host Interface (SHI) Registers */ #define NPCX_SHICFG1 REG8(NPCX_SHI_BASE_ADDR + 0x001) @@ -1510,19 +1053,6 @@ enum ITIM16_MODULE_T { #define NPCX_STATUS REG8(NPCX_SHI_BASE_ADDR + 0x008) #define NPCX_IBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00A) #define NPCX_OBUFSTAT REG8(NPCX_SHI_BASE_ADDR + 0x00B) -#if defined(CHIP_FAMILY_NPCX5) -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n)) -#elif defined(CHIP_FAMILY_NPCX7) -/* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */ -#define NPCX_SHICFG3 REG8(NPCX_SHI_BASE_ADDR + 0x00C) -#define NPCX_SHICFG4 REG8(NPCX_SHI_BASE_ADDR + 0x00D) -#define NPCX_SHICFG5 REG8(NPCX_SHI_BASE_ADDR + 0x00E) -#define NPCX_EVSTAT2 REG8(NPCX_SHI_BASE_ADDR + 0x00F) -#define NPCX_EVENABLE2 REG8(NPCX_SHI_BASE_ADDR + 0x010) -#define NPCX_OBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n)) -#define NPCX_IBUF(n) REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n)) -#endif /* SHI register fields */ #define NPCX_SHICFG1_EN 0 @@ -1558,18 +1088,6 @@ enum ITIM16_MODULE_T { #define NPCX_EVSTAT_IBOR 7 #define NPCX_STATUS_OBES 6 #define NPCX_STATUS_IBFS 7 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_SHICFG3_OBUFLVLDIS 7 -#define NPCX_SHICFG4_IBUFLVLDIS 7 -#define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6) -#define NPCX_SHICFG5_IBUFLVL2DIS 7 -#define NPCX_EVSTAT2_IBHF2 0 -#define NPCX_EVSTAT2_CSNRE 1 -#define NPCX_EVSTAT2_CSNFE 2 -#define NPCX_EVENABLE2_IBHF2EN 0 -#define NPCX_EVENABLE2_CSNREEN 1 -#define NPCX_EVENABLE2_CSNFEEN 2 -#endif /******************************************************************************/ /* Monotonic Counter (MTC) Registers */ @@ -1631,13 +1149,6 @@ enum ITIM16_MODULE_T { #define NPCX_ESPIIE_PLTRSTIE 10 #define NPCX_ESPIIE_AMERRIE 15 #define NPCX_ESPIIE_AMDONEIE 16 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_ESPIIE_BMTXDONEIE 19 -#define NPCX_ESPIIE_PBMRXIE 20 -#define NPCX_ESPIIE_PMSGRXIE 21 -#define NPCX_ESPIIE_BMBURSTERRIE 22 -#define NPCX_ESPIIE_BMBURSTDONEIE 23 -#endif #define NPCX_ESPIWE_IBRSTWE 0 #define NPCX_ESPIWE_CFGUPDWE 1 #define NPCX_ESPIWE_BERRWE 2 @@ -1647,10 +1158,6 @@ enum ITIM16_MODULE_T { #define NPCX_ESPIWE_DFRDWE 7 #define NPCX_ESPIWE_VWUPDWE 8 #define NPCX_ESPIWE_ESPIRSTWE 9 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_ESPIWE_PBMRXWE 20 -#define NPCX_ESPIWE_PMSGRXWE 21 -#endif #define NPCX_ESPISTS_IBRST 0 #define NPCX_ESPISTS_CFGUPD 1 #define NPCX_ESPISTS_BERR 2 @@ -1664,15 +1171,6 @@ enum ITIM16_MODULE_T { #define NPCX_ESPISTS_PLTRST 10 #define NPCX_ESPISTS_AMERR 15 #define NPCX_ESPISTS_AMDONE 16 -#if defined(CHIP_FAMILY_NPCX7) -#define NPCX_ESPISTS_VWUPDW 17 -#define NPCX_ESPISTS_BMTXDONE 19 -#define NPCX_ESPISTS_PBMRX 20 -#define NPCX_ESPISTS_PMSGRX 21 -#define NPCX_ESPISTS_BMBURSTERR 22 -#define NPCX_ESPISTS_BMBURSTDONE 23 -#define NPCX_ESPISTS_ESPIRST_LVL 24 -#endif /* eSPI Virtual Wire channel register fields */ #define NPCX_VWEVSM_WIRE FIELD(0, 4) #define NPCX_VWEVMS_WIRE FIELD(0, 4) @@ -1705,13 +1203,6 @@ enum ITIM16_MODULE_T { #define ESPIIE_PLTRST BIT(NPCX_ESPIIE_PLTRSTIE) #define ESPIIE_AMERR BIT(NPCX_ESPIIE_AMERRIE) #define ESPIIE_AMDONE BIT(NPCX_ESPIIE_AMDONEIE) -#if defined(CHIP_FAMILY_NPCX7) -#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) -#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) -#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) -#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) -#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) -#endif /* eSPI Interrupts for VW */ #define ESPIIE_VW (ESPIIE_VWUPD | ESPIIE_PLTRST) /* eSPI Interrupts for Generic */ @@ -1727,10 +1218,6 @@ enum ITIM16_MODULE_T { #define ESPIWE_DFRD BIT(NPCX_ESPIWE_DFRDWE) #define ESPIWE_VWUPD BIT(NPCX_ESPIWE_VWUPDWE) #define ESPIWE_ESPIRST BIT(NPCX_ESPIWE_ESPIRSTWE) -#if defined(CHIP_FAMILY_NPCX7) -#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) -#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) -#endif /* eSPI Wake-up enable for VW */ #define ESPIWE_VW ESPIWE_VWUPD /* eSPI Wake-up enable for Generic */ @@ -1753,12 +1240,6 @@ enum ITIM16_MODULE_T { #define VWEVMS_PLTRST_EN(p) ((p<<17) & 0x00020000) #define VWEVMS_INT_EN(e) ((e<<18) & 0x00040000) #define VWEVMS_ESPIRST_EN(r) ((r<<19) & 0x00080000) -#if defined(CHIP_FAMILY_NPCX7) -#define VWEVMS_WK_EN(e) ((e<<20) & 0x00100000) -#define VWEVMS_INTWK_EN(e) (VWEVMS_INT_EN(e) | VWEVMS_WK_EN(e)) -#elif defined(CHIP_FAMILY_NPCX5) -#define VWEVMS_INTWK_EN VWEVMS_INT_EN -#endif #define VWEVMS_FIELD(i, n, p, e, r) (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \ VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \ VWEVMS_ESPIRST_EN(r)) @@ -1812,40 +1293,6 @@ enum { NPCX_ESPI_IO_MODE_NONE = 0xFF }; -/* eSPI max supported frequency */ -enum { - NPCX_ESPI_MAXFREQ_20 = 0, - NPCX_ESPI_MAXFREQ_25 = 1, - NPCX_ESPI_MAXFREQ_33 = 2, - NPCX_ESPI_MAXFREQ_50 = 3, -#if defined(CHIP_FAMILY_NPCX5) - NPCX_ESPI_MAXFREQ_66 = 4, -#endif - NPCX_ESPI_MAXFREQ_NOOE = 0xFF -}; - -#if defined(CHIP_FAMILY_NPCX5) - -#if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 -#elif (FMCLK <= 48000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 -#else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 -#endif - -#elif defined(CHIP_FAMILY_NPCX7) - -#if (FMCLK <= 33000000) -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 -#else -#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 -#endif - -#else -#error "Please define NPCX_ESPI_MAXFREQ_MAX for your chip." -#endif - /* VW types */ enum { ESPI_VW_TYPE_INT_EV, /* Interrupt event */ @@ -2149,80 +1596,6 @@ enum { #define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24 /******************************************************************************/ -/* UART registers and functions */ - -#if NPCX_UART_MODULE2 - -#ifdef CHIP_FAMILY_NPCX5 -/* - * To be used as 2nd parameter to NPCX_WK*() macro, table (1st parameter) is - * always 1 == MIWU_TABLE_1. - */ -#define NPCX_UART_WK_GROUP 6 -#define NPCX_UART_WK_BIT 4 -#endif /* CHIP_FAMILY_NPCX5 */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTG_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTC_UART_SL2 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTA_UART_SL1 -#else /* !NPCX_UART_MODULE2 */ - -#ifdef CHIP_FAMILY_NPCX5 -#define NPCX_UART_WK_GROUP 1 -#define NPCX_UART_WK_BIT 0 -#endif /* CHIP_FAMILY_NPCX5 */ -#define NPCX_UART_MIWU_IRQ NPCX_IRQ_WKINTB_1 -#define NPCX_UART_DEVALT NPCX_DEVALT(0x0A) -#define NPCX_UART_DEVALT_SL NPCX_DEVALTA_UART_SL1 -#define NPCX_UART_ALT_DEVALT NPCX_DEVALT(0x0C) -#define NPCX_UART_ALT_DEVALT_SL NPCX_DEVALTC_UART_SL2 -#endif /* NPCX_UART_MODULE2 */ - -#ifdef CHIP_FAMILY_NPCX7 -#define NPCX_UART_WK_GROUP MIWU_GROUP_8 -#define NPCX_UART_WK_BIT 7 -#ifdef NPCX_SECOND_UART -#define NPCX_UART2_WK_GROUP MIWU_GROUP_1 -#define NPCX_UART2_WK_BIT 6 -#endif - -#endif - -/* This routine checks pending bit of GPIO wake-up functionality */ -#if defined(CHIP_FAMILY_NPCX5) -static inline int uart_is_wakeup_from_gpio(void) -{ - return IS_BIT_SET(NPCX_WKPND(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT); -} - -/* This routine checks wake-up functionality from GPIO is enabled or not */ -static inline int uart_is_enable_wakeup(void) -{ - return IS_BIT_SET(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT); -} - -/* This routine clears the pending wake-up from GPIO on UART rx pin */ -static inline void uart_clear_pending_wakeup(void) -{ - SET_BIT(NPCX_WKPCL(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT); -} - -/* This routine enables wake-up functionality from GPIO on UART rx pin */ -static inline void uart_enable_wakeup(int enable) -{ - UPDATE_BIT(NPCX_WKEN(1, NPCX_UART_WK_GROUP), NPCX_UART_WK_BIT, - enable); -} - -/* This routine checks functionality is UART rx or not */ -static inline int npcx_is_uart(void) -{ - return IS_BIT_SET(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL); -} -#endif - -/******************************************************************************/ /* PS/2 registers */ #define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000) #define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002) @@ -2283,4 +1656,14 @@ extern enum gpio_signal hibernate_wake_pins[]; extern int hibernate_wake_pins_used; #endif +#if defined(CHIP_FAMILY_NPCX5) +#include "registers-npcx5.h" +#elif defined(CHIP_FAMILY_NPCX7) +#include "registers-npcx7.h" +#elif defined(CHIP_FAMILY_NPCX9) +#include "registers-npcx9.h" +#else +#error "Unsupported chip family" +#endif + #endif /* __CROS_EC_REGISTERS_H */ |