diff options
| author | Jun Lin <CHLin56@nuvoton.com> | 2022-02-16 14:15:41 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2022-02-25 07:00:38 +0000 |
| commit | 495172f0d7c8055218af9d4ffc21bda038942726 (patch) | |
| tree | 4056825cc7f447d70a8dfa41e99e07c0ffcd8af5 /chip/npcx/registers.h | |
| parent | 45d722959e18a7a865c3cf2c88d8bfc32cdf8c81 (diff) | |
| download | chrome-ec-495172f0d7c8055218af9d4ffc21bda038942726.tar.gz | |
npcx: power down unused modules
This CL sets the power down bit for unused module SDP and I3C to
get better power efficiency.
BUG=b:219388463
BRANCH=none
TEST=pass "make buiilall"
TEST=observe registers by "rw .b 0x4000d008" and "rw .b 0x4000d025"
berfore/after this CL.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Idc399af40588a650e9031c6eadffc70c058d4ac4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3467378
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'chip/npcx/registers.h')
| -rw-r--r-- | chip/npcx/registers.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index f0c241e7f9..5a140e60b8 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -616,7 +616,7 @@ enum { #define NPCX_DISIDL_CTL1 REG8(NPCX_PMC_BASE_ADDR + 0x005) #define NPCX_PWDWN_CTL_ADDR(offset) (((offset) < 6) ? \ (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \ - (NPCX_PMC_BASE_ADDR + 0x024)) + (NPCX_PMC_BASE_ADDR + 0x024 + (offset) - 6)) #define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) /* PMC register fields */ |