diff options
| author | CHLin <CHLIN56@nuvoton.com> | 2018-11-19 15:09:09 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-11-28 05:29:31 -0800 |
| commit | 7491fb02976c649d186d79299bb76b8974c02521 (patch) | |
| tree | 506a14b6a6c28a1cdcb4dfa734f5762e7253b8e5 /chip/npcx/registers.h | |
| parent | 9fd39f0e58ac10abd2e8ae0f0d2734f27776d03e (diff) | |
| download | chrome-ec-7491fb02976c649d186d79299bb76b8974c02521.tar.gz | |
npcx: introduce npcx7m6fc chip definitions and configurations
This CL includes:
1. add CHIP_VARIANT_NPCX7M6FC in the npcx chip configuration files to
define what (RAM, features...) is supported in npcx7m6fc.
2. add the chip id and chip revision id of npcx7m6fc.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change CHIP_VARIANT to npcx7m6fc in board/npcx7_evb/build.mk;
flash image in the internal testing board of npcx7m6fc; make sure the
EC can boot up. Check the chip ID and chip revision ID are correct by
console command "version".
TEST=build and flash the yorp image to the platform; make sure no issues
are found.
Change-Id: Ibcb25fc09b21ec3e5738418af16826035ec81e69
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1343639
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/npcx/registers.h')
| -rw-r--r-- | chip/npcx/registers.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 3d78bf1542..7c2b076912 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -952,9 +952,12 @@ enum { #define NPCX_PWDWN_CTL7_SMB5_PD 0 #define NPCX_PWDWN_CTL7_SMB6_PD 1 #define NPCX_PWDWN_CTL7_SMB7_PD 2 -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M7WB) +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ + defined(CHIP_VARIANT_NPCX7M7WB) #define NPCX_PWDWN_CTL7_ITIM64_PD 5 #define NPCX_PWDWN_CTL7_UART2_PD 6 +#endif +#ifdef CHIP_VARIANT_NPCX7M7WB #define NPCX_PWDWN_CTL7_WOV_PD 7 #endif #endif @@ -1233,7 +1236,8 @@ enum PM_CHANNEL_T { /* BBRAM register fields */ #define NPCX_BKUP_STS_IBBR 7 -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M7WB) +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ + defined(CHIP_VARIANT_NPCX7M7WB) #define NPCX_BKUP_STS_VSBY_STS 1 #define NPCX_BKUP_STS_VCC1_STS 0 #define NPCX_BKUP_STS_ALL_MASK \ |