diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-03-24 08:53:01 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-24 20:43:44 +0000 |
| commit | 81d85531f265579b623f406aab69617d9441e780 (patch) | |
| tree | 65fc9dd42e5eea028b9f2ff9f5bcac1b03e91605 /chip/npcx/registers.h | |
| parent | 65432873c3cf3990d8c473328f0c8ee5744f95a9 (diff) | |
| download | chrome-ec-81d85531f265579b623f406aab69617d9441e780.tar.gz | |
npcx: Fixup eSPI registers
Fixed NPCX_ESPICFG_IOMODE_FIELD and NPCX_ESPICFG_MAXFREQ_FIELD field
length. Added missing bits for ESPICFG and ESPIERR.
BUG=None
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I99d890804ea7eb4394b64684c03d111371000942
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784842
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'chip/npcx/registers.h')
| -rw-r--r-- | chip/npcx/registers.h | 35 |
1 files changed, 32 insertions, 3 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index b9373cd659..3fc3fbe1e9 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -1130,12 +1130,33 @@ enum PM_CHANNEL_T { #define NPCX_ESPICFG_VWCHANEN 1 #define NPCX_ESPICFG_OOBCHANEN 2 #define NPCX_ESPICFG_FLASHCHANEN 3 -#define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 9) -#define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 12) +#define NPCX_ESPICFG_HPCHANEN 4 +#define NPCX_ESPICFG_HVWCHANEN 5 +#define NPCX_ESPICFG_HOOBCHANEN 6 +#define NPCX_ESPICFG_HFLASHCHANEN 7 +#define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2) +#define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3) +#define NPCX_ESPICFG_OPFREQ_FIELD FIELD(17, 3) +#define NPCX_ESPICFG_IOMODESEL_FIELD FIELD(20, 2) +#define NPCX_ESPICFG_ALERT_MODE 22 +#define NPCX_ESPICFG_CRC_CHK 23 #define NPCX_ESPICFG_PCCHN_SUPP 24 #define NPCX_ESPICFG_VWCHN_SUPP 25 #define NPCX_ESPICFG_OOBCHN_SUPP 26 #define NPCX_ESPICFG_FLASHCHN_SUPP 27 +#define NPCX_ESPIERR_INVCMD 0 /* Invalid Command Type */ +#define NPCX_ESPIERR_INVCYC 1 /* Invalid Cycle Type */ +#define NPCX_ESPIERR_CRCERR 2 /* Transaction CRC Error */ +#define NPCX_ESPIERR_ABCOMP 3 /* Abnormal Completion */ +#define NPCX_ESPIERR_PROTERR 4 /* Protocol Error */ +#define NPCX_ESPIERR_BADSIZE 5 /* Bad Size */ +#define NPCX_ESPIERR_NPBADALN 6 /* NPPC Bad Address Alignment */ +#define NPCX_ESPIERR_PCBADALN 7 /* PPC Bad Address Alignment */ +#define NPCX_ESPIERR_UNCMD 9 /* Unsupported Command */ +#define NPCX_ESPIERR_EXTRACYC 10 /* Extra eSPI Clock Cycles */ +#define NPCX_ESPIERR_VWERR 11 /* Virtual Channel Access Error */ +#define NPCX_ESPIERR_UNPBM 14 /* Unsuccessful Bus Completion */ +#define NPCX_ESPIERR_UNFLASH 15 /* Unsuccessful Flash Completion */ #define NPCX_ESPIIE_IBRSTIE 0 #define NPCX_ESPIIE_CFGUPDIE 1 #define NPCX_ESPIIE_BERRIE 2 @@ -1288,11 +1309,19 @@ enum { enum { NPCX_ESPI_IO_MODE_SINGLE = 0, NPCX_ESPI_IO_MODE_DUAL = 1, - NPCX_ESPI_IO_MODE_Quad = 2, + NPCX_ESPI_IO_MODE_QUAD = 2, NPCX_ESPI_IO_MODE_ALL = 3, NPCX_ESPI_IO_MODE_NONE = 0xFF }; +/* eSPI IO mode selected */ +enum { + NPCX_ESPI_IO_MODE_SEL_SINGLE = 0, + NPCX_ESPI_IO_MODE_SEL_DUAL = 1, + NPCX_ESPI_IO_MODE_SEL_QUARD = 2, + NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF +}; + /* VW types */ enum { ESPI_VW_TYPE_INT_EV, /* Interrupt event */ |