npcx: shi: add the support for SHI module version 2

In npcx7, we introduce an enhanced version of Serial Host Interface
(SHI) module. This CL adds the support for it.
It includes:
1. Increase the size of IBF/OBF from 64 bytes to 128 bytes.
2. Add IBULVL/IBFLVL2 in SHICFG4/SHICFG5 which can configure at which
   level the IBF pointer reaches to trigger an interrupt to core.
   The current setting of these two register fields are:
   IBFLVL  - 64 (half full)
   IBFLVL2 - 8 (the size of host command protocol V3 header)
3. Dedicated CS high/low interrupts.
   In old SHI module, the way to generate CS high interrupt event is via
   EOR bit. However, it has a defect that EOR won't be set to 1 when CS
   is de-asserted if there is no SHI CLK generated. It makes the
   handling of glitch condition more complicated.
   In the new SHI module, we introduce the CS high/low interrupts
   (by enabling the CSnFEN/CSnREEN) to make it easier to handle the
   glitch.

The new SHI module is enabled during SHI initialization when the chip
family is npcx7.

BRANCH=none
BUG=none
TEST=No build errors for "make buildall". Test host command
communication is ok between npcx7 EVB and a host emulator.
Make sure the glitch condition can be detected and handled.
Also test the driver on gru, make sure it won't break the operation of
old SHI module.

Change-Id: If297fd32a0ec2c9e340c60c8f1942868fa978fbc
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/607812
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>

1 files changed, 28 insertions, 2 deletions

diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index c201576d68..258ad3b787 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -683,6 +683,11 @@ enum {
 #define NPCX_DEVALTC_UART_SL2            0
 #define NPCX_DEVALTC_SHI_SL              1
 
+#if defined(CHIP_FAMILY_NPCX7)
+/* SHI module version 2 enable bit */
+#define NPCX_DEVALTF_SHI_NEW             7
+#endif
+
 /* Others bit definitions */
 #define NPCX_LFCGCALCNT_LPREG_CTL_EN     1
 
@@ -695,7 +700,6 @@ enum {
 /* DBG register fields */
 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS      7
 
-
 /******************************************************************************/
 /* SMBus Registers */
 #define NPCX_SMBSDA(n)                    REG8(NPCX_SMB_BASE_ADDR(n) + 0x000)
@@ -1348,9 +1352,19 @@ enum ITIM16_MODULE_T {
 #define NPCX_STATUS                       REG8(NPCX_SHI_BASE_ADDR + 0x008)
 #define NPCX_IBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00A)
 #define NPCX_OBUFSTAT                     REG8(NPCX_SHI_BASE_ADDR + 0x00B)
-#define NPCX_ADVCFG                       REG8(NPCX_SHI_BASE_ADDR + 0x00E)
+#if defined(CHIP_FAMILY_NPCX5)
 #define NPCX_OBUF(n)                      REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
 #define NPCX_IBUF(n)                      REG8(NPCX_SHI_BASE_ADDR + 0x060 + (n))
+#elif defined(CHIP_FAMILY_NPCX7)
+/* Serial Host Interface (SHI) Registers - only available on SHI Version 2 */
+#define NPCX_SHICFG3                      REG8(NPCX_SHI_BASE_ADDR + 0x00C)
+#define NPCX_SHICFG4                      REG8(NPCX_SHI_BASE_ADDR + 0x00D)
+#define NPCX_SHICFG5                      REG8(NPCX_SHI_BASE_ADDR + 0x00E)
+#define NPCX_EVSTAT2                      REG8(NPCX_SHI_BASE_ADDR + 0x00F)
+#define NPCX_EVENABLE2                    REG8(NPCX_SHI_BASE_ADDR + 0x010)
+#define NPCX_OBUF(n)                      REG8(NPCX_SHI_BASE_ADDR + 0x020 + (n))
+#define NPCX_IBUF(n)                      REG8(NPCX_SHI_BASE_ADDR + 0x0A0 + (n))
+#endif
 
 /* SHI register fields */
 #define NPCX_SHICFG1_EN                  0
@@ -1386,6 +1400,18 @@ enum ITIM16_MODULE_T {
 #define NPCX_EVSTAT_IBOR                 7
 #define NPCX_STATUS_OBES                 6
 #define NPCX_STATUS_IBFS                 7
+#if defined(CHIP_FAMILY_NPCX7)
+#define NPCX_SHICFG3_OBUFLVLDIS          7
+#define NPCX_SHICFG4_IBUFLVLDIS          7
+#define NPCX_SHICFG5_IBUFLVL2            FIELD(0, 6)
+#define NPCX_SHICFG5_IBUFLVL2DIS         7
+#define NPCX_EVSTAT2_IBHF2               0
+#define NPCX_EVSTAT2_CSNRE               1
+#define NPCX_EVSTAT2_CSNFE               2
+#define NPCX_EVENABLE2_IBHF2EN           0
+#define NPCX_EVENABLE2_CSNREEN           1
+#define NPCX_EVENABLE2_CSNFEEN           2
+#endif
 
 /******************************************************************************/
 /* Monotonic Counter (MTC) Registers */