diff options
| author | Jun Lin <CHLin56@nuvoton.com> | 2021-09-10 13:36:17 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-09-17 10:11:45 +0000 |
| commit | 20222d48571fa44c76fdb0ededd0ed042e9f8244 (patch) | |
| tree | cf3980940a27dadd13e2912d1eb92724f4287c1e /chip/npcx/registers.h | |
| parent | cec869cd82bee052362a1e3e292854163a25fd88 (diff) | |
| download | chrome-ec-20222d48571fa44c76fdb0ededd0ed042e9f8244.tar.gz | |
npcx: correct the image copies indication bits for npcx9
In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'chip/npcx/registers.h')
| -rw-r--r-- | chip/npcx/registers.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 374e9d58ba..f0c241e7f9 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -175,14 +175,6 @@ #define NPCX_IRQ_COUNT 64 /******************************************************************************/ -/* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) - -/* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 - -/******************************************************************************/ /* High Frequency Clock Generator (HFCG) registers */ #define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) #define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002) |