diff options
| author | Caveh Jalali <caveh@chromium.org> | 2018-02-08 14:50:50 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-02-15 00:10:45 -0800 |
| commit | bee58e5d3e03d714641ec799ff519cd6abde735a (patch) | |
| tree | 52c1951d707bd4fd0eb1aebeae34535feb58d763 /chip/npcx/registers.h | |
| parent | 9b83436b147482593e4770b1c7daabfdd0fabc8b (diff) | |
| download | chrome-ec-bee58e5d3e03d714641ec799ff519cd6abde735a.tar.gz | |
npcx: set eSPI speed to max supported by hardware
the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up
to 66MHz. so, set the max speed to whatever the hardware can actually
do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's
not even define it in the npcx7 case.
BUG=b:72838699, b:71859563
BRANCH=none
TEST="make buildall" passes; boots on meowth
Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910321
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'chip/npcx/registers.h')
| -rw-r--r-- | chip/npcx/registers.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 855adfb32d..d451eb04c9 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -1666,10 +1666,20 @@ enum { NPCX_ESPI_MAXFREQ_25 = 1, NPCX_ESPI_MAXFREQ_33 = 2, NPCX_ESPI_MAXFREQ_50 = 3, +#if defined(CHIP_FAMILY_NPCX5) NPCX_ESPI_MAXFREQ_66 = 4, +#endif NPCX_ESPI_MAXFREQ_NOOE = 0xFF }; +#if defined(CHIP_FAMILY_NPCX5) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 +#elif defined(CHIP_FAMILY_NPCX7) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#else +#error "Please define NPCX_ESPI_MAXFREQ_MAX for your chip." +#endif + /* VW types */ enum { ESPI_VW_TYPE_INT_EV, /* Interrupt event */ |