nuc: Add SHI driver for arm-based platform in chip folder.

Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter

Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>

1 files changed, 66 insertions, 0 deletions

diff --git a/chip/npcx/rom_chip.h b/chip/npcx/rom_chip.h
new file mode 100644
index 0000000000..6d635f6c4d
--- /dev/null
+++ b/chip/npcx/rom_chip.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_ROM_CHIP_H_
+#define __CROS_EC_ROM_CHIP_H_
+
+/******************************************************************************/
+/*
+ * Enumerations of ROM api functions
+ */
+enum API_SIGN_OPTIONS_T {
+	SIGN_NO_CHECK = 0,
+	SIGN_CRC_CHECK = 1,
+};
+
+enum API_RETURN_STATUS_T {
+	/* Successful download */
+	API_RET_STATUS_OK = 0,
+	/* Address is outside of flash or not 4 bytes aligned. */
+	API_RET_STATUS_INVALID_SRC_ADDR = 1,
+	/* Address is outside of RAM or not 4 bytes aligned. */
+	API_RET_STATUS_INVALID_DST_ADDR = 2,
+	/* Size is 0 or not 4 bytes aligned. */
+	API_RET_STATUS_INVALID_SIZE = 3,
+	/* Flash Address + Size is out of flash. */
+	API_RET_STATUS_INVALID_SIZE_OUT_OF_FLASH = 4,
+	/* RAM Address + Size is out of RAM. */
+	API_RET_STATUS_INVALID_SIZE_OUT_OF_RAM = 5,
+	/* Wrong sign option. */
+	API_RET_STATUS_INVALID_SIGN = 6,
+	/* Error during Code copy. */
+	API_RET_STATUS_COPY_FAILED = 7,
+	/* Execution Address is outside of RAM */
+	API_RET_STATUS_INVALID_EXE_ADDR = 8,
+	/* Bad CRC value */
+	API_RET_STATUS_INVALID_SIGNATURE = 9,
+};
+
+/******************************************************************************/
+/*
+ * Macro functions of ROM api functions
+ */
+#define ADDR_DOWNLOAD_FROM_FLASH (*(volatile uint32_t *) 0x40)
+#define download_from_flash(src_offset, dest_addr, size, sign, exe_addr, \
+	status) \
+	(((download_from_flash_ptr) ADDR_DOWNLOAD_FROM_FLASH) \
+	(src_offset, dest_addr, size, sign, exe_addr, status))
+
+/******************************************************************************/
+/*
+ * Declarations of ROM api functions
+ */
+typedef void (*download_from_flash_ptr) (
+	uint32_t src_offset, /* The offset of the data to be downloaded */
+	uint32_t dest_addr,  /* The address of the downloaded data in the RAM*/
+	uint32_t size,       /* Number of bytes to download */
+	enum API_SIGN_OPTIONS_T sign, /* Need CRC check or not */
+	uint32_t exe_addr, /* jump to this address after download if not zero */
+	enum API_RETURN_STATUS_T *status /* Status fo download */
+);
+
+
+
+#endif /* __CROS_EC_ROM_CHIP_H_ */