diff options
| author | CHLin <CHLIN56@nuvoton.com> | 2019-04-19 17:47:24 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-27 01:36:52 -0700 |
| commit | 7a87d4b5c984cc24937944b4cbcd8cd7f3b4fd0b (patch) | |
| tree | 7685d1af5f5113570b0d2a3b5eacdb1d01c202dc /chip/npcx/sib_chip.h | |
| parent | 0c71c4748699f5f2cb1423ffc07d4c852d04b3fc (diff) | |
| download | chrome-ec-7a87d4b5c984cc24937944b4cbcd8cd7f3b4fd0b.tar.gz | |
npcx: disable the selection of JTAG0 signals due to strap
It was observed that pressing recovery key combination + the other
keys, some keys on the keyboard become invalid after system reboots.
(see b:129908668 for more detail.)
It is because the hardware strap pin for JTAG0 signals is
unintentionally triggered. This CL reverts the selection of JTAG signals
and set them back to keyboard scan function at system initialization.
The revert applies to all real platforms except npcx_evbs.
BRANCH=none
BUG=b:129908668
TEST=pass "make buildall"
TEST=Press the specific key combination, after the system reboots,
the keyboard function works normally. On npcx EVBs, the JTAG0 is still
functional.
Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1575887
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip/npcx/sib_chip.h')
| -rw-r--r-- | chip/npcx/sib_chip.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/chip/npcx/sib_chip.h b/chip/npcx/sib_chip.h new file mode 100644 index 0000000000..2341f219b4 --- /dev/null +++ b/chip/npcx/sib_chip.h @@ -0,0 +1,23 @@ +/* + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* NPCX-specific SIB module for Chrome EC */ + +/* Super-IO index and register definitions */ +#define INDEX_SID 0x20 +#define INDEX_CHPREV 0x24 +#define INDEX_SRID 0x27 + +#define SIO_OFFSET 0x4E + +/* Super-IO register write function */ +void sib_write_reg(uint8_t io_offset, uint8_t index_value, + uint8_t io_data); +/* Super-IO register read function */ +uint8_t sib_read_reg(uint8_t io_offset, uint8_t index_value); +/* Emulate host to read Keyboard I/O */ +uint8_t sib_read_kbc_reg(uint8_t io_offset); + |