npcx: modify the npcxspiflash little firmware to support UUT

The original ec_npcxspiflash lfw is used by the openocd to program SPI
flash via Servo JTAG. In order to support UUT mode to program SPI flash,
this CL modified the lfw with the following changes:
1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming.
2. The npcx_monitor will read the first 4 bytes from the area of monitor
header. If the monitor identifies the first 4 bytes is a UUT tag, it
will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of
monitor header. Otherwise, it will read parameter from the general
register r0/r1 which will be restored by openocd script in advance.
3. Add monitor_hdr.c to generate the monitor header binary files
(monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled.

The memory layout to restore the reuqired binaries are listed below:
ec firmware(RO/RW) - the start address of Code RAM area.
monitor header - 0x200C3000
npcx_monitor - 0x200C3020

BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=Follow instructions in CL:826763; make sure the ec firmware is
updated and ec can boot up.
CQ-DEPEND=CL:828341

Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/826909
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>

1 files changed, 37 insertions, 0 deletions

diff --git a/chip/npcx/spiflashfw/monitor_hdr.c b/chip/npcx/spiflashfw/monitor_hdr.c
new file mode 100644
index 0000000000..b875eb4e86
--- /dev/null
+++ b/chip/npcx/spiflashfw/monitor_hdr.c
@@ -0,0 +1,37 @@
+/* Copyright (c) 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * NPCX SoC spi flash update tool -  monitor firmware header
+ */
+
+#include "config.h"
+#include "npcx_monitor.h"
+
+const struct monitor_header_tag monitor_hdr = {
+	/* 0x00: TAG = 0xA5075001 */
+	NPCX_MONITOR_UUT_TAG,
+	/* 0x04: Size·of·the·EC image·be·programmed.
+	 * Default = code RAM size
+	 */
+	NPCX_PROGRAM_MEMORY_SIZE,
+	/*
+	 * 0x08: The start of RAM address to store the EC image, which will be
+	 * programed into the SPI flash.
+	 */
+	CONFIG_PROGRAM_MEMORY_BASE,
+	/* 0x0C:The Flash start address to be programmed*/
+#ifdef SECTION_IS_RO
+	/* Default: RO image is programed from the start of SPI flash */
+	CONFIG_EC_PROTECTED_STORAGE_OFF,
+#else
+	/* Default: RW image is programed from the half of SPI flash */
+	CONFIG_EC_WRITABLE_STORAGE_OFF,
+#endif
+	/* 0x10: Maximum allowable flash clock frequency */
+	0,
+	/* 0x11: SPI Flash read mode */
+	0,
+	/* 0x12: Reserved */
+	0,
+};