diff options
| author | Ian Chao <mlchao@nuvoton.com> | 2015-07-09 14:53:00 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-07-25 01:22:32 +0000 |
| commit | 14bd917343489c09033f0f9c97e7951d5cb2aeec (patch) | |
| tree | 1722f9d92f5ffb2525eebec68f86b1aab06b3e71 /chip/npcx/spiflashfw | |
| parent | 7de0037538bd0016c9202ad289655cbf4f4d90aa (diff) | |
| download | chrome-ec-14bd917343489c09033f0f9c97e7951d5cb2aeec.tar.gz | |
nuc:
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/npcx/spiflashfw')
| -rw-r--r-- | chip/npcx/spiflashfw/ec_npcxflash.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chip/npcx/spiflashfw/ec_npcxflash.c b/chip/npcx/spiflashfw/ec_npcxflash.c index 41e833b273..ccaff16872 100644 --- a/chip/npcx/spiflashfw/ec_npcxflash.c +++ b/chip/npcx/spiflashfw/ec_npcxflash.c @@ -273,6 +273,9 @@ sspi_flash_upload(int spi_offset, int spi_size) NPCX_WDSDM = 0x61; NPCX_WDSDM = 0x63; + /* UMA Unlock */ + CLEAR_BIT(NPCX_UMA_ECTS, NPCX_UMA_ECTS_UMA_LOCK); + /* Set pinmux first */ sspi_flash_pinmux(1); |