diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-05 17:27:37 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:32 -0700 |
| commit | 558c465165acf494905fa59c822c7190b4646899 (patch) | |
| tree | a20a512da9d8aed29cb46d99b8df0b8bb0ab5714 /chip/npcx/spiflashfw | |
| parent | d58e54730c03290296df5bb65cb84264e4b2facc (diff) | |
| download | chrome-ec-558c465165acf494905fa59c822c7190b4646899.tar.gz | |
cleanup: Remove CDRAM / CODERAM CONFIGs
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/spiflashfw')
| -rw-r--r-- | chip/npcx/spiflashfw/ec_npcxflash.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/chip/npcx/spiflashfw/ec_npcxflash.c b/chip/npcx/spiflashfw/ec_npcxflash.c index cc97f69e5a..ef62ac97dc 100644 --- a/chip/npcx/spiflashfw/ec_npcxflash.c +++ b/chip/npcx/spiflashfw/ec_npcxflash.c @@ -6,8 +6,10 @@ */ #include <stdint.h> + +#include "config.h" #include "registers.h" -#include "config_chip.h" +#include "util.h" /*****************************************************************************/ /* spi flash internal functions */ @@ -241,7 +243,7 @@ int sspi_flash_verify(int offset, int size, const char *data) int sspi_flash_get_image_used(const char *fw_base) { const uint8_t *image; - int size = CONFIG_CDRAM_SIZE; /* maximum size is 128KB */ + int size = MAX(CONFIG_RO_SIZE, CONFIG_RW_SIZE); /* max size is 128KB */ image = (const uint8_t *)fw_base; /* @@ -265,7 +267,7 @@ sspi_flash_upload(int spi_offset, int spi_size) /* * Flash image has been uploaded to Code RAM */ - const char *image_base = (const char *)CONFIG_CDRAM_BASE; + const char *image_base = (const char *)CONFIG_PROGRAM_MEMORY_BASE; uint32_t sz_image = spi_size; /* Unlock & stop watchdog */ |