diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2017-02-15 17:06:37 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-02-25 14:23:20 -0800 |
| commit | 23bc38414ade30fb3e72ae8beefb657b47ca8288 (patch) | |
| tree | a3bd50f2e039cee14e71a453190b4daaa5fc61c2 /chip/npcx/system_chip.h | |
| parent | b7f8d9df654945827d6a21332e140ddecb8bdd1b (diff) | |
| download | chrome-ec-23bc38414ade30fb3e72ae8beefb657b47ca8288.tar.gz | |
pd: Store PD active state in battery-backed memory
Our previous idea to cut Rd for many reset cases cannot work if cr50
consistently resets the EC by asserting the reset pin shortly after
power-on. Therefore, make a decision based upon whether battery-backed
memory indicates we previously negotiated a PD power contract as a sink.
If we previously did not negotiate a contract, or if power was removed
from the device (causing battery-backed memory to wipe) then we can
assume that we don't have an active power contract.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, run "cutoff" on the console, reattach AC, and verify
device successfully wakes. Also verify Rp is dropped on console 'reboot'
and F3 + power from RW.
Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443356
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/npcx/system_chip.h')
| -rw-r--r-- | chip/npcx/system_chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h index b15c030dc4..c32c163c6a 100644 --- a/chip/npcx/system_chip.h +++ b/chip/npcx/system_chip.h @@ -13,6 +13,8 @@ enum bbram_data_index { BBRM_DATA_INDEX_SCRATCHPAD = 0, /* General-purpose scratchpad */ BBRM_DATA_INDEX_SAVED_RESET_FLAGS = 4, /* Saved reset flags */ BBRM_DATA_INDEX_WAKE = 8, /* Wake reasons for hibernate */ + BBRM_DATA_INDEX_PD0 = 12, /* USB-PD saved port0 state */ + BBRM_DATA_INDEX_PD1 = 13, /* USB-PD saved port1 state */ BBRM_DATA_INDEX_VBNVCNTXT = 16, /* VbNvContext for ARM arch */ BBRM_DATA_INDEX_RAMLOG = 32, /* RAM log for Booter */ }; |