diff options
author | Mulin Chao <mlchao@nuvoton.com> | 2016-01-15 11:17:43 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-01-20 20:36:53 -0800 |
commit | ebd29d455793d048daadc2dcfef7e26edee9d46b (patch) | |
tree | 2a5052c13cd2c9bfe3460e75cec449ab44c2ee71 /chip/npcx/uart.c | |
parent | 17ffa6b1abdec63015054623226a09c60c38a1ee (diff) | |
download | chrome-ec-ebd29d455793d048daadc2dcfef7e26edee9d46b.tar.gz |
nuc: Adjust core clock from 16/12 MHz to 15/13 MHz.
We found the deviation of 115200 UART baud-rate is too large when core
clock is 16 or 12MHz. It causes failure during FAFT since sometime EC
could not receive correct commands to proceed test. We adjusted core
clock from 16/12 to 15/13 to reduce the deviation of 115200. Both of
them have run FAFT and stress tests for weeks and no UART issues were
found.
Since the lowest source clock of i2c is 6.5MHz, we modified tSCLL, tSCLH
and hold time directly for better i2c timing when freq is 400K. And if
freq is 100K, we introduced normal mode to handle it.
Modified sources:
1. clock.c: Adjust core clock from 16/12 MHz to 15/13 MHz.
2. clock_chip.h: Set target core clock as 15 MHz.
3. uart.c: Add baud-rate support for 15/13 MHz.
4. register.h: Add new register definitions of SMBus.
5. i2c.c: Modified tSCLL, tSCLH and hold time directly for better i2c
timing.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ie5d22e87875c064b49338046c99a178f8fadf32b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322320
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/npcx/uart.c')
-rw-r--r-- | chip/npcx/uart.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c index c25b2fd01e..5b47110835 100644 --- a/chip/npcx/uart.c +++ b/chip/npcx/uart.c @@ -171,11 +171,14 @@ static void uart_config(void) #elif (OSC_CLK == 24000000) NPCX_UPSR = 0x60; NPCX_UBAUD = 0x00; -#elif (OSC_CLK == 16000000) - NPCX_UPSR = 0x10; - NPCX_UBAUD = 0x02; +#elif (OSC_CLK == 15000000) + NPCX_UPSR = 0x38; + NPCX_UBAUD = 0x00; +#elif (OSC_CLK == 13000000) + NPCX_UPSR = 0x30; + NPCX_UBAUD = 0x00; #else -#error "Unsupported FMCLK Clock Frequency" +#error "Unsupported Core Clock Frequency" #endif |