diff options
author | Mulin Chao <mlchao@nuvoton.com> | 2016-01-29 18:03:20 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-02-06 01:57:58 -0800 |
commit | f700e3bb0ea187bae315ff925f59c8eab05fb446 (patch) | |
tree | 1a0b6eba415c58d906299f554c9d6b0b1e415e79 /chip/npcx/uart.c | |
parent | 4ec554dd8fbdd47871dcd04374fb04018b24b7b5 (diff) | |
download | chrome-ec-f700e3bb0ea187bae315ff925f59c8eab05fb446.tar.gz |
nuc: Add support for CONFIG_LOW_POWER_S0.
To get better power consumption in S0, we add FW support for
CONFIG_LOW_POWER_S0.
Before entering deep idle in S0, we must enable Host interrupt to wake up
EC if it needs to service LPC bus.
This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h
to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of
PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of
PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal.
In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR
since preload counter is changed by __hw_clock_source_set all the time.
We also found there're no event set if it's deadline is over 32 bits but
current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if
ITIM32 expires, FW set an event for ITIM32 after process_timers().
Modified sources:
1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition.
2. clock.c: Enable Host interrupt for LPC.
3. clock.c: Disable LP_WK_CTL for better power consumption.
4. gpio.c: Add ISR for Host interrupt.
5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed.
6. register.h: Add uart_clear_pending_wakeup function.
7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow.
8. fan.c: Enable deep sleep if duty cycle is zero.
9. include/system.h: Add SLEEP_MASK_FAN for fan control loop.
10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the
instruction pipeline.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/324651
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/npcx/uart.c')
-rw-r--r-- | chip/npcx/uart.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c index 5b47110835..b9f06f42dc 100644 --- a/chip/npcx/uart.c +++ b/chip/npcx/uart.c @@ -66,6 +66,9 @@ void uart_tx_flush(void) /* Wait for transmit FIFO empty */ while (!(NPCX_UICTRL & 0x01)) ; + /* Wait for transmitting completed */ + while (NPCX_USTAT & 0x40) + ; } int uart_tx_ready(void) @@ -101,9 +104,6 @@ void uart_write_char(char c) ; NPCX_UTBUF = c; -#ifdef CONFIG_LOW_POWER_IDLE - clock_refresh_console_in_use(); -#endif } int uart_read_char(void) |