diff options
| author | CHLin <CHLin56@nuvoton.com> | 2020-09-09 11:22:57 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-25 16:56:49 +0000 |
| commit | 1639bd944d3a70479f18edcd0ee47fc6026f8127 (patch) | |
| tree | 7ef7906a58f1820f87c38b4fa254c3a0b2595464 /chip/npcx/uart.c | |
| parent | cd2ce1213b08f8a2365407d39a005918190888b8 (diff) | |
| download | chrome-ec-1639bd944d3a70479f18edcd0ee47fc6026f8127.tar.gz | |
npcx: make required changes in some modules for npcx9
1. Functions are supported in npcx7 but npcx5 are guarded by:
"#if defined(CHIP_FAMILY_NPCX7)."
In npcx9, most of these functions are inherited. Change the guard to:
"#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7"
2. Configure APB4DIV in clock.c
3. In npcx5/7, the host interface type (HIF_TYP_SEL in the
DEVCNT register) is updated by booter after VCC1 Power-Up reset
according to VHIF voltage. In npcx9, the booter will not do this
anymore. Set the HIF_TYP_SEL filed at initialization in lpc.c anyway
to cover to all chip family.
4. Configure power down registers appropriately.
5 add symbolic links:
i2c-npcx9.c -> i2c_npcx5.c
system-npcx9.c -> system-npcx7.c
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=with related CLs, build and flash image on the npcx7/9 EVB and
yorp, no symptom occurs.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I17a71b7b90435d4a3ff75aac18bf2640b5b15515
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402843
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'chip/npcx/uart.c')
| -rw-r--r-- | chip/npcx/uart.c | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c index 1e4d88f789..efe991ec0b 100644 --- a/chip/npcx/uart.c +++ b/chip/npcx/uart.c @@ -85,17 +85,34 @@ void npcx_gpio2uart(void) { #ifdef CONFIG_UART_PAD_SWITCH if (pad == UART_ALTERNATE_PAD) { +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN__SL); + SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL); + CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL); + CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL); +#else SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL); CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL); +#endif return; } #endif +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL); + SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL); + CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN_SL); + CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL); +#else SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL); CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL); +#endif -#if !NPCX_UART_MODULE2 && defined(CHIP_FAMILY_NPCX7) - /* UART module 1 belongs to KSO since wake-up functionality in npcx7. */ +#if !NPCX_UART_MODULE2 && (NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7) + /* + * UART module 1 belongs to KSO since wake-up functionality in npcx7 + * and later chips. + */ CLEAR_BIT(NPCX_DEVALT(0x09), NPCX_DEVALT9_NO_KSO09_SL); #endif } |