nuc: Add all IC specific drivers of NPCX5M5G

Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.

Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
   in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
   with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742

1 files changed, 142 insertions, 0 deletions

diff --git a/chip/npcx/watchdog.c b/chip/npcx/watchdog.c
new file mode 100644
index 0000000000..411488877a
--- /dev/null
+++ b/chip/npcx/watchdog.c
@@ -0,0 +1,142 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Watchdog driver */
+
+#include "clock.h"
+#include "common.h"
+#include "console.h"
+#include "registers.h"
+#include "hwtimer_chip.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "timer.h"
+#include "task.h"
+#include "util.h"
+#include "watchdog.h"
+
+/* WDCNT value for watchdog period */
+#define WDCNT_VALUE   ((CONFIG_WATCHDOG_PERIOD_MS*INT_32K_CLOCK) / (1024*1000))
+/* Delay counter time for print watchdog info through UART */
+#define WDCNT_DELAY   0x10
+
+
+void watchdog_init_warning_timer(void)
+{
+	/* init watchdog timer first */
+	init_hw_timer(ITIM_WDG_NO, ITIM16_SOURCE_CLOCK_32K);
+
+	/*
+	 * prescaler to TIMER_TICK
+	 * Ttick_unit = (PRE_8+1) * T32k
+	 * PRE_8 = (Ttick_unit/T32K) - 1
+	 * Unit: 1 msec
+	 */
+	NPCX_ITPRE(ITIM_WDG_NO)  = DIV_ROUND_NEAREST(1000*INT_32K_CLOCK,
+							 SECOND) - 1;
+
+	/* ITIM count down : event expired*/
+	NPCX_ITCNT16(ITIM_WDG_NO) = CONFIG_WATCHDOG_PERIOD_MS-1;
+	/* Event module enable */
+	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITIM16_ITEN);
+	/* Enable interrupt of ITIM */
+	task_enable_irq(ITIM16_INT(ITIM_WDG_NO));
+}
+
+
+void watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
+{
+	int  wd_cnt;
+	/* Clear timeout status for event */
+	SET_BIT(NPCX_ITCTS(ITIM_WDG_NO), NPCX_ITIM16_TO_STS);
+
+	/* Read watchdog counter from TWMWD */
+	wd_cnt = NPCX_TWMWD;
+#if DEBUG_WDG
+	ccprintf("WD (%d)\r\n", wd_cnt);
+#endif
+	if (wd_cnt <= WDCNT_DELAY)
+		watchdog_trace(excep_lr, excep_sp);
+}
+
+/* ISR for watchdog warning naked will keep SP & LR */
+void IRQ_HANDLER(ITIM16_INT(ITIM_WDG_NO))(void) __attribute__((naked));
+void IRQ_HANDLER(ITIM16_INT(ITIM_WDG_NO))(void)
+		{
+	/* Naked call so we can extract raw LR and SP */
+	asm volatile("mov r0, lr\n"
+			"mov r1, sp\n"
+			/* Must push registers in pairs to keep 64-bit aligned
+			 * stack for ARM EABI.  This also conveninently saves
+			 * R0=LR so we can pass it to task_resched_if_needed. */
+			"push {r0, lr}\n"
+			"bl watchdog_check\n"
+			"pop {r0, lr}\n"
+			"b task_resched_if_needed\n");
+		}
+const struct irq_priority IRQ_PRIORITY(ITIM16_INT(ITIM_WDG_NO))
+__attribute__((section(".rodata.irqprio")))
+= {ITIM16_INT(ITIM_WDG_NO), 0};
+/* put the watchdog at the highest priority */
+
+void watchdog_reload(void)
+{
+	/* Disable watchdog interrupt */
+	task_disable_irq(ITIM16_INT(ITIM_WDG_NO));
+
+#if 1 /* mark this for testing watchdog */
+	/* Touch watchdog & reset software counter */
+	NPCX_WDSDM = 0x5C;
+#endif
+
+	/* Enable watchdog interrupt */
+	task_enable_irq(ITIM16_INT(ITIM_WDG_NO));
+}
+DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
+
+int watchdog_init(void)
+{
+#if SUPPORT_WDG
+	/* Keep prescaler ratio timer0 clock to 1:1024 */
+	NPCX_TWCP = 0x0A;
+	/* Keep prescaler ratio watchdog clock to 1:1 */
+	NPCX_WDCP = 0;
+
+	/* Clear watchdog reset status initially*/
+	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_WDRST_STS);
+
+	/* Reset TWCFG */
+	NPCX_TWCFG = 0;
+	/* Watchdog touch by writing 5Ch to WDSDM */
+	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDSDME);
+	/* Select T0IN clock as watchdog prescaler clock */
+	SET_BIT(NPCX_TWCFG, NPCX_TWCFG_WDCT0I);
+	/* Disable early touch functionality */
+	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_TESDIS);
+
+	/*
+	 * Set WDCNT initial reload value and T0OUT timeout period
+	 * 1. Watchdog clock source is 32768/1024 Hz and disable T0OUT.
+	 * 2. ITIM16 will be issued to check WDCNT is under WDCNT_DELAY or not
+	 * 3. Set RST to upload TWDT0 & WDCNT
+	 */
+	/* Set WDCNT --> WDCNT=0 will generate watchdog reset */
+	NPCX_WDCNT = WDCNT_VALUE + WDCNT_DELAY;
+
+	/* Disable interrupt */
+	interrupt_disable();
+	/* Reload TWDT0/WDCNT */
+	SET_BIT(NPCX_T0CSR, NPCX_T0CSR_RST);
+	/* Wait for timer is loaded and restart */
+	while (IS_BIT_SET(NPCX_T0CSR, NPCX_T0CSR_RST))
+		;
+	/* Enable interrupt */
+	interrupt_enable();
+
+	/* Init watchdog warning timer */
+	watchdog_init_warning_timer();
+#endif
+	return EC_SUCCESS;
+}