npcx: change chip variants of npcx7 series for better clarification.

In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w
to npcx7m7wb for better clafiication since it introduced new parameter
"b" for chip generation in the same family series.

In new npcx7 series naming rule, it follows:
Format: NPCX7(M)(N)(G/K/F)(B/C)
  param M: 8: 128-pins package, 9: 144-pins package
  param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size
  param G/K/F/W: Google EC depends on specific features.
  param B/C: Chip generation in npcx7. (Generation A is ignored. It
             follows nameing rule in npcx5.)

The all chip variants of npcx7 used in boards are also listed below:
 npcx7m6g  - for npcx7 ec without internal flash on npcx_evb.
 npcx7m6f  - for npcx7 ec with internal flash.
 npcx7m6fb - for npcx7 ec with internal flash, enhanced features.
 npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV.

BRANCH=none
BUG=none
TEST=No build errors for npcx7 series.

Change-Id: I896ee33209efa5d7157c90515005db5f36318c76
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1025471
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
index 5892f490a8..090a66ebdf 100644
--- a/chip/npcx/wov.c
+++ b/chip/npcx/wov.c
@@ -261,7 +261,7 @@ static enum ec_error_list wov_calc_pll_div_l(uint32_t i2s_clk_freq,
 
 	/*
 	 * The code below implemented the “PLL setting option” table as
-	 * describe in the NPCX7m7w specification document.
+	 * describe in the NPCX7m7wb specification document.
 	 * - Total_div is VCO frequency in MHz / 12 MHz
 	 * - d_f is the Feedback Divider
 	 * - d_in is the Input Divider (PLL_INDV)