diff options
| author | Wealian <whliao@nuvoton.corp-partner.google.com> | 2020-03-06 16:30:57 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-03-11 04:49:29 +0000 |
| commit | 2e94c27c3866debba24369adc1c31908f4d7d74a (patch) | |
| tree | 7866b2f3b165a37831338214dcd02fdb9e30904b /chip/npcx | |
| parent | 18500f672d0dcc76c79c8975a014293d7c7e94db (diff) | |
| download | chrome-ec-2e94c27c3866debba24369adc1c31908f4d7d74a.tar.gz | |
npcx/lpc: Don't enable PM channel OBE interrupt at init
Like what is done in the CL:2073282 for KBC. OBE interrupt enable
shouldn't be set in lpc_init(). The default value of OBF bit is 0.
It's will send a spurious interrupt to NVIC.
BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Test host command on yorp overnight by the following command:
"while true; do ectool version; done"
Change-Id: If9172a18b737f2d6c3c7930fcdc9aaf5ef4c8533
Signed-off-by: Wealian <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2091133
Reviewed-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'chip/npcx')
| -rw-r--r-- | chip/npcx/lpc.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 4e297654b8..8572ce497d 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -784,7 +784,6 @@ static void lpc_init(void) /* Turn on PMC2 for Host Command usage */ SET_BIT(NPCX_HIPMCTL(PMC_HOST_CMD), 0); - SET_BIT(NPCX_HIPMCTL(PMC_HOST_CMD), 1); /* * Set required control value (avoid setting HOSTWAIT bit at this stage) @@ -808,9 +807,9 @@ static void lpc_init(void) /* * Turn on enhance mode on PM channel-1, - * enable OBE/IBF core interrupt + * enable IBF core interrupt */ - NPCX_HIPMCTL(PMC_ACPI) |= 0x83; + NPCX_HIPMCTL(PMC_ACPI) |= 0x81; /* Normally Polarity IRQ1,12 type (level + high) setting */ NPCX_HIIRQC = 0x00; |