common: bit change 1 << constants with BIT(constants)

Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.

Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]

BUG=None
BRANCH=None
TEST=None

Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

12 files changed, 88 insertions, 88 deletions

diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c
index d996695dfc..8c544c5970 100644
--- a/chip/npcx/cec.c
+++ b/chip/npcx/cec.c
@@ -791,7 +791,7 @@ void cec_isr(void)
 	/* Retrieve events NPCX_TECTRL_TAXND */
 	events = GET_FIELD(NPCX_TECTRL(mdl), FIELD(0, 4));
 
-	if (events & (1 << NPCX_TECTRL_TAPND)) {
+	if (events & BIT(NPCX_TECTRL_TAPND)) {
 		/* Capture event */
 		cec_event_cap();
 	} else {
@@ -801,11 +801,11 @@ void cec_isr(void)
 		 * happening, since we will get both events in the
 		 * edge-trigger case
 		 */
-		if (events & (1 << NPCX_TECTRL_TCPND))
+		if (events & BIT(NPCX_TECTRL_TCPND))
 			cec_event_timeout();
 	}
 	/* Oneshot timer, a transfer has been initiated from AP */
-	if (events & (1 << NPCX_TECTRL_TDPND)) {
+	if (events & BIT(NPCX_TECTRL_TDPND)) {
 		tmr2_stop();
 		cec_event_tx();
 	}
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index 97f52963fd..7512e5a399 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -66,7 +66,7 @@
 /* Default use UART1 as console */
 #define CONFIG_CONSOLE_UART    0
 
-#define GPIO_PIN(port, index) GPIO_##port, (1 << index)
+#define GPIO_PIN(port, index) GPIO_##port, BIT(index)
 #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m)
 
 #endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
index 21766701a0..d092327aed 100644
--- a/chip/npcx/espi.c
+++ b/chip/npcx/espi.c
@@ -532,7 +532,7 @@ void espi_interrupt(void)
 	 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
 	 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
 	 */
-	mask = NPCX_ESPIIE | (1 << NPCX_ESPISTS_VWUPDW);
+	mask = NPCX_ESPIIE | BIT(NPCX_ESPISTS_VWUPDW);
 #else
 	mask = NPCX_ESPIIE;
 #endif
diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c
index 252b915e45..8a76043d3d 100644
--- a/chip/npcx/gpio.c
+++ b/chip/npcx/gpio.c
@@ -313,7 +313,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func)
 
 	/* check each bit from mask  */
 	for (pin = 0; pin < 8; pin++)
-		if (mask & (1 << pin))
+		if (mask & BIT(pin))
 			gpio_alt_sel(port, pin, func);
 }
 
diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c
index 76f1822a94..a201a75219 100644
--- a/chip/npcx/hwtimer.c
+++ b/chip/npcx/hwtimer.c
@@ -20,7 +20,7 @@
 
 /* Depth of event timer */
 #define TICK_EVT_DEPTH         16 /* Depth of event timer Unit: bits */
-#define TICK_EVT_INTERVAL      (1 << TICK_EVT_DEPTH) /* Unit: us */
+#define TICK_EVT_INTERVAL      BIT(TICK_EVT_DEPTH) /* Unit: us */
 #define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */
 #define TICK_EVT_MAX_CNT     (TICK_EVT_INTERVAL - 1) /* Maximum event counter */
 
diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c
index 97a563c53f..9ed18b3739 100644
--- a/chip/npcx/keyboard_raw.c
+++ b/chip/npcx/keyboard_raw.c
@@ -101,7 +101,7 @@ test_mockable void keyboard_raw_drive_column(int col)
 	}
 	/* Set KBSOUT to zero to detect key-press */
 	else if (col == KEYBOARD_COLUMN_ALL) {
-		mask = ~((1 << keyboard_cols) - 1);
+		mask = ~(BIT(keyboard_cols) - 1);
 #ifdef CONFIG_KEYBOARD_COL2_INVERTED
 		gpio_set_level(GPIO_KBD_KSO2, 1);
 #endif
@@ -114,7 +114,7 @@ test_mockable void keyboard_raw_drive_column(int col)
 		else
 			gpio_set_level(GPIO_KBD_KSO2, 0);
 #endif
-		mask = ~(1 << col_out);
+		mask = ~BIT(col_out);
 	}
 
 	/* Set KBSOUT */
@@ -158,6 +158,6 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, keyboard_raw_interrupt, 5);
 
 int keyboard_raw_is_input_low(int port, int id)
 {
-	return (NPCX_PDIN(port) & (1 << id)) == 0;
+	return (NPCX_PDIN(port) & BIT(id)) == 0;
 }
 
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 971512ec72..74d7f29d99 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -981,7 +981,7 @@ static void lpc_init(void)
 	CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL);
 	/* Set SMIB/SCIB to make sure SMI/SCI are high at init */
 	NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI)
-			| (1 << NPCX_HIPMIC_SMIB) | (1 << NPCX_HIPMIC_SCIB);
+			| BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB);
 #ifndef CONFIG_SCI_GPIO
 	/*
 	 * Allow SMI/SCI generated from PM module.
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 7c812e5da2..c13395eaa4 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -1005,44 +1005,44 @@ enum NPCX_PMC_PWDWN_CTL_T {
 };
 
 /* TODO: set PD masks based upon actual peripheral usage */
-#define CGC_KBS_MASK     (1 << NPCX_PWDWN_CTL1_KBS_PD)
-#define CGC_UART_MASK    (1 << NPCX_PWDWN_CTL1_UART_PD)
-#define CGC_FAN_MASK     ((1 << NPCX_PWDWN_CTL1_MFT1_PD) | \
-			 (1 << NPCX_PWDWN_CTL1_MFT2_PD))
-#define CGC_FIU_MASK     (1 << NPCX_PWDWN_CTL1_FIU_PD)
+#define CGC_KBS_MASK     BIT(NPCX_PWDWN_CTL1_KBS_PD)
+#define CGC_UART_MASK    BIT(NPCX_PWDWN_CTL1_UART_PD)
+#define CGC_FAN_MASK     (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | \
+			 BIT(NPCX_PWDWN_CTL1_MFT2_PD))
+#define CGC_FIU_MASK     BIT(NPCX_PWDWN_CTL1_FIU_PD)
 #if defined(CHIP_FAMILY_NPCX5)
-#define CGC_I2C_MASK     ((1 << NPCX_PWDWN_CTL3_SMB0_PD) | \
-			 (1 << NPCX_PWDWN_CTL3_SMB1_PD) | \
-			 (1 << NPCX_PWDWN_CTL3_SMB2_PD) | \
-			 (1 << NPCX_PWDWN_CTL3_SMB3_PD))
+#define CGC_I2C_MASK     (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
+			 BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+			 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
+			 BIT(NPCX_PWDWN_CTL3_SMB3_PD))
 #elif defined(CHIP_FAMILY_NPCX7)
-#define CGC_I2C_MASK     ((1 << NPCX_PWDWN_CTL3_SMB0_PD) | \
-			 (1 << NPCX_PWDWN_CTL3_SMB1_PD) | \
-			 (1 << NPCX_PWDWN_CTL3_SMB2_PD) | \
-			 (1 << NPCX_PWDWN_CTL3_SMB3_PD) | \
-			 (1 << NPCX_PWDWN_CTL3_SMB4_PD))
-#define CGC_I2C_MASK2    ((1 << NPCX_PWDWN_CTL7_SMB5_PD) | \
-			 (1 << NPCX_PWDWN_CTL7_SMB6_PD) | \
-			 (1 << NPCX_PWDWN_CTL7_SMB7_PD))
+#define CGC_I2C_MASK     (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \
+			 BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \
+			 BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \
+			 BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \
+			 BIT(NPCX_PWDWN_CTL3_SMB4_PD))
+#define CGC_I2C_MASK2    (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \
+			 BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \
+			 BIT(NPCX_PWDWN_CTL7_SMB7_PD))
 #ifdef NPCX_SECOND_UART
-#define CGC_UART2_MASK   (1 << NPCX_PWDWN_CTL7_UART2_PD)
+#define CGC_UART2_MASK   BIT(NPCX_PWDWN_CTL7_UART2_PD)
 #endif
 #ifdef NPCX_WOV_SUPPORT
-#define CGC_WOV_MASK     (1 << NPCX_PWDWN_CTL7_WOV_PD)
+#define CGC_WOV_MASK     BIT(NPCX_PWDWN_CTL7_WOV_PD)
 #endif
 #endif
-#define CGC_ADC_MASK     (1 << NPCX_PWDWN_CTL4_ADC_PD)
-#define CGC_PECI_MASK    (1 << NPCX_PWDWN_CTL4_PECI_PD)
-#define CGC_SPI_MASK     (1 << NPCX_PWDWN_CTL4_SPIP_PD)
-#define CGC_TIMER_MASK   ((1 << NPCX_PWDWN_CTL4_ITIM1_PD) | \
-			 (1 << NPCX_PWDWN_CTL4_ITIM2_PD) | \
-			 (1 << NPCX_PWDWN_CTL4_ITIM3_PD))
-#define CGC_LPC_MASK     ((1 << NPCX_PWDWN_CTL5_C2HACC_PD) | \
-			 (1 << NPCX_PWDWN_CTL5_SHM_REG_PD) | \
-			 (1 << NPCX_PWDWN_CTL5_SHM_PD) | \
-			 (1 << NPCX_PWDWN_CTL5_DP80_PD) | \
-			 (1 << NPCX_PWDWN_CTL5_MSWC_PD))
-#define CGC_ESPI_MASK    (1 << NPCX_PWDWN_CTL6_ESPI_PD)
+#define CGC_ADC_MASK     BIT(NPCX_PWDWN_CTL4_ADC_PD)
+#define CGC_PECI_MASK    BIT(NPCX_PWDWN_CTL4_PECI_PD)
+#define CGC_SPI_MASK     BIT(NPCX_PWDWN_CTL4_SPIP_PD)
+#define CGC_TIMER_MASK   (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | \
+			 BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \
+			 BIT(NPCX_PWDWN_CTL4_ITIM3_PD))
+#define CGC_LPC_MASK     (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | \
+			 BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \
+			 BIT(NPCX_PWDWN_CTL5_SHM_PD) | \
+			 BIT(NPCX_PWDWN_CTL5_DP80_PD) | \
+			 BIT(NPCX_PWDWN_CTL5_MSWC_PD))
+#define CGC_ESPI_MASK    BIT(NPCX_PWDWN_CTL6_ESPI_PD)
 
 /******************************************************************************/
 /* Flash Interface Unit (FIU) Registers */
@@ -1242,11 +1242,11 @@ enum PM_CHANNEL_T {
 #define NPCX_BKUP_STS_VSBY_STS           1
 #define NPCX_BKUP_STS_VCC1_STS           0
 #define NPCX_BKUP_STS_ALL_MASK \
-	((1 << NPCX_BKUP_STS_IBBR) | (1 << NPCX_BKUP_STS_VSBY_STS) | \
-	(1 << NPCX_BKUP_STS_VCC1_STS))
+	(BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \
+	BIT(NPCX_BKUP_STS_VCC1_STS))
 #define NPCX_BBRAM_SIZE                 128  /* Size of BBRAM */
 #else
-#define NPCX_BKUP_STS_ALL_MASK (1 << NPCX_BKUP_STS_IBBR)
+#define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR)
 #define NPCX_BBRAM_SIZE                  64  /* Size of BBRAM */
 #endif
 
@@ -1625,32 +1625,32 @@ enum ITIM16_MODULE_T {
 #define ENABLE_ESPI_CHAN(ch)             SET_BIT(NPCX_ESPICFG, ch)
 #define DISABLE_ESPI_CHAN(ch)            CLEAR_BIT(NPCX_ESPICFG, ch)
 /* ESPI Slave Channel Support Definitions */
-#define ESPI_SUPP_CH_PC                  (1 << NPCX_ESPICFG_PCCHN_SUPP)
-#define ESPI_SUPP_CH_VM                  (1 << NPCX_ESPICFG_VWCHN_SUPP)
-#define ESPI_SUPP_CH_OOB                 (1 << NPCX_ESPICFG_OOBCHN_SUPP)
-#define ESPI_SUPP_CH_FLASH               (1 << NPCX_ESPICFG_FLASHCHN_SUPP)
+#define ESPI_SUPP_CH_PC                  BIT(NPCX_ESPICFG_PCCHN_SUPP)
+#define ESPI_SUPP_CH_VM                  BIT(NPCX_ESPICFG_VWCHN_SUPP)
+#define ESPI_SUPP_CH_OOB                 BIT(NPCX_ESPICFG_OOBCHN_SUPP)
+#define ESPI_SUPP_CH_FLASH               BIT(NPCX_ESPICFG_FLASHCHN_SUPP)
 #define ESPI_SUPP_CH_ALL                 (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | \
 					  ESPI_SUPP_CH_OOB | ESPI_SUPP_CH_FLASH)
 /* ESPI Interrupts Enable Definitions */
-#define ESPIIE_IBRST                     (1 << NPCX_ESPIIE_IBRSTIE)
-#define ESPIIE_CFGUPD                    (1 << NPCX_ESPIIE_CFGUPDIE)
-#define ESPIIE_BERR                      (1 << NPCX_ESPIIE_BERRIE)
-#define ESPIIE_OOBRX                     (1 << NPCX_ESPIIE_OOBRXIE)
-#define ESPIIE_FLASHRX                   (1 << NPCX_ESPIIE_FLASHRXIE)
-#define ESPIIE_SFLASHRD                  (1 << NPCX_ESPIIE_SFLASHRDIE)
-#define ESPIIE_PERACC                    (1 << NPCX_ESPIIE_PERACCIE)
-#define ESPIIE_DFRD                      (1 << NPCX_ESPIIE_DFRDIE)
-#define ESPIIE_VWUPD                     (1 << NPCX_ESPIIE_VWUPDIE)
-#define ESPIIE_ESPIRST                   (1 << NPCX_ESPIIE_ESPIRSTIE)
-#define ESPIIE_PLTRST                    (1 << NPCX_ESPIIE_PLTRSTIE)
-#define ESPIIE_AMERR                     (1 << NPCX_ESPIIE_AMERRIE)
-#define ESPIIE_AMDONE                    (1 << NPCX_ESPIIE_AMDONEIE)
+#define ESPIIE_IBRST                     BIT(NPCX_ESPIIE_IBRSTIE)
+#define ESPIIE_CFGUPD                    BIT(NPCX_ESPIIE_CFGUPDIE)
+#define ESPIIE_BERR                      BIT(NPCX_ESPIIE_BERRIE)
+#define ESPIIE_OOBRX                     BIT(NPCX_ESPIIE_OOBRXIE)
+#define ESPIIE_FLASHRX                   BIT(NPCX_ESPIIE_FLASHRXIE)
+#define ESPIIE_SFLASHRD                  BIT(NPCX_ESPIIE_SFLASHRDIE)
+#define ESPIIE_PERACC                    BIT(NPCX_ESPIIE_PERACCIE)
+#define ESPIIE_DFRD                      BIT(NPCX_ESPIIE_DFRDIE)
+#define ESPIIE_VWUPD                     BIT(NPCX_ESPIIE_VWUPDIE)
+#define ESPIIE_ESPIRST                   BIT(NPCX_ESPIIE_ESPIRSTIE)
+#define ESPIIE_PLTRST                    BIT(NPCX_ESPIIE_PLTRSTIE)
+#define ESPIIE_AMERR                     BIT(NPCX_ESPIIE_AMERRIE)
+#define ESPIIE_AMDONE                    BIT(NPCX_ESPIIE_AMDONEIE)
 #if defined(CHIP_FAMILY_NPCX7)
-#define ESPIIE_BMTXDONE                  (1 << NPCX_ESPIIE_BMTXDONEIE)
-#define ESPIIE_PBMRX                     (1 << NPCX_ESPIIE_PBMRXIE)
-#define ESPIIE_PMSGRX                    (1 << NPCX_ESPIIE_PMSGRXIE)
-#define ESPIIE_BMBURSTERR                (1 << NPCX_ESPIIE_BMBURSTERRIE)
-#define ESPIIE_BMBURSTDONE               (1 << NPCX_ESPIIE_BMBURSTDONEIE)
+#define ESPIIE_BMTXDONE                  BIT(NPCX_ESPIIE_BMTXDONEIE)
+#define ESPIIE_PBMRX                     BIT(NPCX_ESPIIE_PBMRXIE)
+#define ESPIIE_PMSGRX                    BIT(NPCX_ESPIIE_PMSGRXIE)
+#define ESPIIE_BMBURSTERR                BIT(NPCX_ESPIIE_BMBURSTERRIE)
+#define ESPIIE_BMBURSTDONE               BIT(NPCX_ESPIIE_BMBURSTDONEIE)
 #endif
 /* eSPI Interrupts for VW */
 #define ESPIIE_VW                        (ESPIIE_VWUPD | ESPIIE_PLTRST)
@@ -1658,18 +1658,18 @@ enum ITIM16_MODULE_T {
 #define ESPIIE_GENERIC                   (ESPIIE_IBRST | ESPIIE_CFGUPD | \
 					  ESPIIE_BERR | ESPIIE_ESPIRST)
 /* ESPI Wake-up Enable Definitions */
-#define ESPIWE_IBRST                     (1 << NPCX_ESPIWE_IBRSTWE)
-#define ESPIWE_CFGUPD                    (1 << NPCX_ESPIWE_CFGUPDWE)
-#define ESPIWE_BERR                      (1 << NPCX_ESPIWE_BERRWE)
-#define ESPIWE_OOBRX                     (1 << NPCX_ESPIWE_OOBRXWE)
-#define ESPIWE_FLASHRX                   (1 << NPCX_ESPIWE_FLASHRXWE)
-#define ESPIWE_PERACC                    (1 << NPCX_ESPIWE_PERACCWE)
-#define ESPIWE_DFRD                      (1 << NPCX_ESPIWE_DFRDWE)
-#define ESPIWE_VWUPD                     (1 << NPCX_ESPIWE_VWUPDWE)
-#define ESPIWE_ESPIRST                   (1 << NPCX_ESPIWE_ESPIRSTWE)
+#define ESPIWE_IBRST                     BIT(NPCX_ESPIWE_IBRSTWE)
+#define ESPIWE_CFGUPD                    BIT(NPCX_ESPIWE_CFGUPDWE)
+#define ESPIWE_BERR                      BIT(NPCX_ESPIWE_BERRWE)
+#define ESPIWE_OOBRX                     BIT(NPCX_ESPIWE_OOBRXWE)
+#define ESPIWE_FLASHRX                   BIT(NPCX_ESPIWE_FLASHRXWE)
+#define ESPIWE_PERACC                    BIT(NPCX_ESPIWE_PERACCWE)
+#define ESPIWE_DFRD                      BIT(NPCX_ESPIWE_DFRDWE)
+#define ESPIWE_VWUPD                     BIT(NPCX_ESPIWE_VWUPDWE)
+#define ESPIWE_ESPIRST                   BIT(NPCX_ESPIWE_ESPIRSTWE)
 #if defined(CHIP_FAMILY_NPCX7)
-#define ESPIWE_PBMRX                     (1 << NPCX_ESPIWE_PBMRXWE)
-#define ESPIWE_PMSGRX                    (1 << NPCX_ESPIWE_PMSGRXWE)
+#define ESPIWE_PBMRX                     BIT(NPCX_ESPIWE_PBMRXWE)
+#define ESPIWE_PMSGRX                    BIT(NPCX_ESPIWE_PMSGRXWE)
 #endif
 /* eSPI  Wake-up enable for VW */
 #define ESPIWE_VW                        ESPIWE_VWUPD
diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c
index 2e061ad2c2..2f084c597e 100644
--- a/chip/npcx/shi.c
+++ b/chip/npcx/shi.c
@@ -661,7 +661,7 @@ void shi_int_handler(void)
 	/* SHI CS pin is asserted in EVSTAT2 */
 	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNFE)) {
 		/* clear CSNFE bit */
-		NPCX_EVSTAT2 = (1 << NPCX_EVSTAT2_CSNFE);
+		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNFE);
 		DEBUG_CPRINTF("CSNFE-");
 		/*
 		 * BUSY bit is set when SHI_CS is asserted. If not, leave it for
@@ -688,7 +688,7 @@ void shi_int_handler(void)
 	 */
 	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNRE)) {
 		/* Clear pending bit of CSNRE */
-		NPCX_EVSTAT2 = (1 << NPCX_EVSTAT2_CSNRE);
+		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNRE);
 #else
 	if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_EOR)) {
 #endif
@@ -784,7 +784,7 @@ void shi_int_handler(void)
 	 */
 	if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_IBHF2)) {
 		/* Clear IBHF2 */
-		NPCX_EVSTAT2 = (1 << NPCX_EVSTAT2_IBHF2);
+		NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_IBHF2);
 		DEBUG_CPRINTF("HDR-");
 		/* Disable second IBF interrupt and start to parse header */
 		shi_sec_ibf_int_enable(0);
diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c
index 579b2a1321..6b0e5157ea 100644
--- a/chip/npcx/system-npcx7.c
+++ b/chip/npcx/system-npcx7.c
@@ -22,7 +22,7 @@
 
 /* Macros for last 32K ram block */
 #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1)
-#define RAM_PD_MASK  (~(1 << LAST_RAM_BLK))
+#define RAM_PD_MASK  (BIT(LAST_RAM_BLK) - 1)
 
 /*****************************************************************************/
 /* IC specific low-level driver depends on chip series */
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index b9d3367d91..4b2f55ddb4 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -117,7 +117,7 @@ static int bbram_valid(enum bbram_data_index index, int bytes)
 
 	/* Check BBRAM is valid */
 	if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) {
-		NPCX_BKUP_STS = (1 << NPCX_BKUP_STS_IBBR);
+		NPCX_BKUP_STS = BIT(NPCX_BKUP_STS_IBBR);
 		panic_printf("IBBR set: BBRAM corrupted!\n");
 		return 0;
 	}
@@ -693,8 +693,8 @@ void system_pre_init(void)
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8;
 
 	pwdwn6 = 0x70 |
-		(1 << NPCX_PWDWN_CTL6_ITIM6_PD) |
-		(1 << NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
+		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
+		BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
 #if !defined(CONFIG_HOSTCMD_ESPI)
 	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
 #endif
diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c
index d7d46e849f..692e75419f 100644
--- a/chip/npcx/uartn.c
+++ b/chip/npcx/uartn.c
@@ -188,9 +188,9 @@ static void uartn_set_fifo_mode(uint8_t uart_num)
 	/* Enable the UART FIFO mode */
 	SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD);
 	/* Disable all Tx interrupts */
-	NPCX_UFTCTL(uart_num) &= ~((1 << NPCX_UFTCTL_TEMPTY_LVL_EN) |
-					(1 << NPCX_UFTCTL_TEMPTY_EN) |
-					(1 << NPCX_UFTCTL_NXIMPEN));
+	NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
+					BIT(NPCX_UFTCTL_TEMPTY_EN) |
+					BIT(NPCX_UFTCTL_NXIMPEN));
 }
 
 #endif