Revert "npcx: workaround the bug that SHM data read via eSPI may be corrupted"

This reverts commit ddbfe690e294e595c6ed3511dcf417410d9b2804.

Reason for revert: Causes move cursor movements to be choppy, and device
  to be very unresponsive during flashrom EC operations.

Original change's description:
> npcx: workaround the bug that SHM data read via eSPI may be corrupted
>
> In eSPI systems, when the Host performs a data read from the Shared
> Memory space, the returned data may be corrupted. This is a result of
> the Core-to-Host access enable bit being toggled (by toggling CSAE bit
> in SIBCTRL register) during an eSPI transaction.
>
> The workaround in this CL is to set CSAE bit to 1 during initialization
> and remove the toggling of CSAE bit from other EC firmware code.
> (i.e., let the CSAE bit be always 1.)
>
> BRANCH=none
> BUG=none
> TEST=No build errors for make buildall. Flash poppy ec image, make sure
> it can boot to OS. Run "ectool version" over 100000 times, no error
> occurs.
>
> Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe
> Signed-off-by: CHLin <CHLIN56@nuvoton.com>
> Reviewed-on: https://chromium-review.googlesource.com/590396
> Commit-Ready: Shawn N <shawnn@chromium.org>
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: Shawn N <shawnn@chromium.org>

BUG=b:64730183
TEST=flashrom -p ec -r ecr.bin, device still responsive.

Change-Id: Idaeef2707df990b2441a77a15807698d41018449
Reviewed-on: https://chromium-review.googlesource.com/618366
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

1 files changed, 12 insertions, 3 deletions

diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 556276dbc8..7770609c1b 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -368,6 +368,8 @@ uint8_t lpc_sib_read_kbc_reg(uint8_t io_offset)
 
 	/* Lock host keyboard module */
 	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
+	/* Enable Core-to-Host Modules Access */
+	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* Verify Core read/write to host modules is not in progress */
 	lpc_sib_wait_host_read_done();
 	lpc_sib_wait_host_write_done();
@@ -386,6 +388,8 @@ uint8_t lpc_sib_read_kbc_reg(uint8_t io_offset)
 
 	/* Disable Core access to keyboard module */
 	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_HIKBDAE);
+	/* Disable Core-to-Host Modules Access */
+	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* unlock host keyboard module */
 	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKHIKBD);
 
@@ -720,6 +724,8 @@ void lpc_sib_write_reg(uint8_t io_offset, uint8_t index_value,
 
 	/* Lock host CFG module */
 	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
+	/* Enable Core-to-Host Modules Access */
+	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* Enable Core access to CFG module */
 	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
 	/* Verify Core read/write to host modules is not in progress */
@@ -742,6 +748,8 @@ void lpc_sib_write_reg(uint8_t io_offset, uint8_t index_value,
 
 	/* Disable Core access to CFG module */
 	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
+	/* Disable Core-to-Host Modules Access */
+	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* unlock host CFG  module */
 	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
 
@@ -758,6 +766,8 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value)
 
 	/* Lock host CFG module */
 	SET_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
+	/* Enable Core-to-Host Modules Access */
+	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* Enable Core access to CFG module */
 	SET_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
 	/* Verify Core read/write to host modules is not in progress */
@@ -782,6 +792,8 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value)
 
 	/* Disable Core access to CFG module */
 	CLEAR_BIT(NPCX_CRSMAE, NPCX_CRSMAE_CFGAE);
+	/* Disable Core-to-Host Modules Access */
+	CLEAR_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
 	/* unlock host CFG  module */
 	CLEAR_BIT(NPCX_LKSIOHA, NPCX_LKSIOHA_LKCFG);
 
@@ -794,9 +806,6 @@ uint8_t lpc_sib_read_reg(uint8_t io_offset, uint8_t index_value)
 /* For LPC host register initial via SIB module */
 void host_register_init(void)
 {
-	/* Enable Core-to-Host Modules Access */
-	SET_BIT(NPCX_SIBCTRL, NPCX_SIBCTRL_CSAE);
-
 	/* enable ACPI*/
 	lpc_sib_write_reg(SIO_OFFSET, 0x07, 0x11);
 	lpc_sib_write_reg(SIO_OFFSET, 0x30, 0x01);