npcx: make required changes in some modules for npcx9

1. Functions are supported in npcx7 but npcx5 are guarded by:
  "#if defined(CHIP_FAMILY_NPCX7)."
In npcx9, most of these functions are inherited. Change the guard to:
  "#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7"
2. Configure APB4DIV in clock.c
3. In npcx5/7, the host interface type (HIF_TYP_SEL in the
   DEVCNT register) is updated by booter after VCC1 Power-Up reset
   according to VHIF voltage. In npcx9, the booter will not do this
   anymore. Set the HIF_TYP_SEL filed at initialization in lpc.c anyway
   to cover to all chip family.
4. Configure power down registers appropriately.
5 add symbolic links:
  i2c-npcx9.c -> i2c_npcx5.c
  system-npcx9.c -> system-npcx7.c

BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=with related CLs, build and flash image on the npcx7/9 EVB and
yorp, no symptom occurs.

Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I17a71b7b90435d4a3ff75aac18bf2640b5b15515
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402843
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>

10 files changed, 69 insertions, 23 deletions

diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index 287583232a..0f8f737401 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -121,12 +121,16 @@ void clock_init(void)
 #if defined(CHIP_FAMILY_NPCX5)
 	NPCX_HFCGP  = (FPRED << 4);
 	NPCX_HFCBCD = (NPCX_HFCBCD & 0xF0) | (APB1DIV | (APB2DIV << 2));
-#elif defined(CHIP_FAMILY_NPCX7)
+#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	NPCX_HFCGP   = ((FPRED << 4) | AHB6DIV);
 	NPCX_HFCBCD  = (FIUDIV << 4);
 	NPCX_HFCBCD1 = (APB1DIV | (APB2DIV << 4));
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	NPCX_HFCBCD2 = (APB3DIV | (APB4DIV << 4));
+#else
 	NPCX_HFCBCD2 = APB3DIV;
 #endif
+#endif
 
 	/* Notify modules of frequency change */
 	hook_notify(HOOK_FREQ_CHANGE);
@@ -159,7 +163,7 @@ void clock_turbo(void)
 	 */
 	NPCX_HFCBCD = NPCX_HFCBCD & 0xF3;
 }
-#elif defined(CHIP_FAMILY_NPCX7)
+#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 void clock_turbo(void)
 {
 	/*
@@ -225,7 +229,7 @@ int clock_get_apb2_freq(void)
 /**
  * Return the current APB3 clock frequency in Hz.
  */
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 int clock_get_apb3_freq(void)
 {
 	return NPCX_APB_CLOCK(3);
@@ -343,7 +347,7 @@ void __idle(void)
 #if defined(CHIP_FAMILY_NPCX5)
 			/* UART-rx(console) become to GPIO (NONE INT mode) */
 			clock_uart2gpio();
-#elif defined(CHIP_FAMILY_NPCX7)
+#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 			uartn_wui_en(CONFIG_CONSOLE_UART);
 #endif
 
diff --git a/chip/npcx/clock_chip.h b/chip/npcx/clock_chip.h
index 4bf7aca5b1..702b55c52a 100644
--- a/chip/npcx/clock_chip.h
+++ b/chip/npcx/clock_chip.h
@@ -40,7 +40,7 @@
 #define APB1DIV 3 /* Default APB1 clock = CORE_CLK/4 */
 /* APB2 clock divider */
 #define APB2DIV 0 /* Let APB2 = CORE_CLK since UART baudrate tolerance */
-#elif defined(CHIP_FAMILY_NPCX7)
+#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 /*
  * NPCX7 clock tree: (Please refer Figure 58. for more information.)
  *
@@ -81,6 +81,10 @@
 #define APB2DIV 5 /* APB2 clock = OSC_CLK/6 */
 /* APB3 clock divider */
 #define APB3DIV 5 /* APB3 clock = OSC_CLK/6 */
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+/* APB4 clock divider */
+#define APB4DIV 5 /* APB4 clock = OSC_CLK/6 */
+#endif
 #endif
 
 /* Get APB clock freq */
@@ -133,9 +137,9 @@
 #if (OSC_CLK > 50000000)
 #error "Unsupported OSC_CLK on NPCX5 series!"
 #endif
-#elif defined(CHIP_FAMILY_NPCX7)
+#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 #if (OSC_CLK > 100000000)
-#error "Unsupported OSC_CLK on NPCX7 series!"
+#error "Unsupported OSC_CLK on NPCX series!"
 #endif
 #endif
 
diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c
index 43de2002da..9073838bd6 100644
--- a/chip/npcx/espi.c
+++ b/chip/npcx/espi.c
@@ -531,7 +531,7 @@ void espi_interrupt(void)
 	int chan;
 	uint32_t mask, status;
 
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	/*
 	 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
 	 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
diff --git a/chip/npcx/i2c-npcx9.c b/chip/npcx/i2c-npcx9.c
new file mode 120000
index 0000000000..b1b16a3198
--- /dev/null
+++ b/chip/npcx/i2c-npcx9.c
@@ -0,0 +1 @@
+i2c-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/i2c.c b/chip/npcx/i2c.c
index 8814f53994..9d72c80c71 100644
--- a/chip/npcx/i2c.c
+++ b/chip/npcx/i2c.c
@@ -144,7 +144,7 @@ const unsigned int i2c_1m_timing_used = ARRAY_SIZE(i2c_1m_timings);
 /* IRQ for each port */
 const uint32_t i2c_irqs[I2C_CONTROLLER_COUNT] = {
 		NPCX_IRQ_SMB1, NPCX_IRQ_SMB2, NPCX_IRQ_SMB3, NPCX_IRQ_SMB4,
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 		NPCX_IRQ_SMB5, NPCX_IRQ_SMB6, NPCX_IRQ_SMB7, NPCX_IRQ_SMB8,
 #endif
 };
@@ -853,7 +853,7 @@ void i2c0_interrupt(void) { handle_interrupt(0); }
 void i2c1_interrupt(void) { handle_interrupt(1); }
 void i2c2_interrupt(void) { handle_interrupt(2); }
 void i2c3_interrupt(void) { handle_interrupt(3); }
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 void i2c4_interrupt(void) { handle_interrupt(4); }
 void i2c5_interrupt(void) { handle_interrupt(5); }
 void i2c6_interrupt(void) { handle_interrupt(6); }
@@ -864,7 +864,7 @@ DECLARE_IRQ(NPCX_IRQ_SMB1, i2c0_interrupt, 4);
 DECLARE_IRQ(NPCX_IRQ_SMB2, i2c1_interrupt, 4);
 DECLARE_IRQ(NPCX_IRQ_SMB3, i2c2_interrupt, 4);
 DECLARE_IRQ(NPCX_IRQ_SMB4, i2c3_interrupt, 4);
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 DECLARE_IRQ(NPCX_IRQ_SMB5, i2c4_interrupt, 4);
 DECLARE_IRQ(NPCX_IRQ_SMB6, i2c5_interrupt, 4);
 DECLARE_IRQ(NPCX_IRQ_SMB7, i2c6_interrupt, 4);
@@ -1020,7 +1020,7 @@ static void i2c_freq_changed(void)
 		int ctrl = i2c_port_to_controller(i2c_ports[i].port);
 		int scl_freq;
 
-#ifdef CHIP_FAMILY_NPCX7
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 		/*
 		 * SMB0/1/4/5/6/7 use APB3 clock
 		 * SMB2/3 use APB2 clock
@@ -1106,7 +1106,7 @@ void i2c_init(void)
 	/* Enable clock for I2C peripheral */
 	clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK,
 			CGC_MODE_RUN | CGC_MODE_SLEEP);
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	clock_enable_peripheral(CGC_OFFSET_I2C2, CGC_I2C_MASK2,
 			CGC_MODE_RUN | CGC_MODE_SLEEP);
 #endif
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index b287ad8c36..d614c1788b 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -721,8 +721,16 @@ static void lpc_init(void)
 	/* Enable clock for LPC peripheral */
 	clock_enable_peripheral(CGC_OFFSET_LPC, CGC_LPC_MASK,
 			CGC_MODE_RUN | CGC_MODE_SLEEP);
+	/*
+	 * In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT
+	 * register) is updated by booter after VCC1 Power-Up reset according to
+	 * VHIF voltage.
+	 * In npcx9, the booter will not do this anymore. The HIF_TYP_SEL
+	 * field should be set by firmware.
+	 */
 #ifdef CONFIG_HOSTCMD_ESPI
-	/* Initialize eSPI IP */
+	/* Initialize eSPI module */
+	NPCX_DEVCNT |= 0x08;
 	espi_init();
 #else
 	/* Switching to LPC interface */
diff --git a/chip/npcx/system-npcx9.c b/chip/npcx/system-npcx9.c
new file mode 120000
index 0000000000..48088614a0
--- /dev/null
+++ b/chip/npcx/system-npcx9.c
@@ -0,0 +1 @@
+system-npcx7.c
\ No newline at end of file
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index d62e360229..645113baa7 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -466,7 +466,7 @@ static void system_set_gpios_and_wakeup_inputs_hibernate(void)
 		}
 	}
 
-#if defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 	/* Disable MIWU 2 group 6 inputs which used for the additional GPIOs */
 	NPCX_WKEN(MIWU_TABLE_2, MIWU_GROUP_6)  = 0x00;
 	NPCX_WKPCL(MIWU_TABLE_2, MIWU_GROUP_6) = 0xFF;
@@ -609,7 +609,7 @@ void system_set_rtc_alarm(uint32_t seconds, uint32_t microseconds)
 	SET_BIT(NPCX_WTC, NPCX_WTC_WIE);
 
 	/* Enable MTC interrupt */
-	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
+	task_enable_irq(NPCX_IRQ_MTC);
 
 	/* Enable wake-up input sources & clear pending bit */
 	NPCX_WKPCL(MIWU_TABLE_0, MTC_WUI_GROUP)  |= MTC_WUI_MASK;
@@ -627,7 +627,7 @@ void system_reset_rtc_alarm(void)
 	SET_BIT(NPCX_WTC, NPCX_WTC_PTO);
 
 	/* Disable MTC interrupt */
-	task_disable_irq(NPCX_IRQ_MTC_WKINTAD_0);
+	task_disable_irq(NPCX_IRQ_MTC);
 }
 
 /*
@@ -654,7 +654,7 @@ uint32_t system_get_rtc_alarm(void)
  */
 void system_enable_hib_interrupt(void)
 {
-	task_enable_irq(NPCX_IRQ_MTC_WKINTAD_0);
+	task_enable_irq(NPCX_IRQ_MTC);
 }
 
 void system_hibernate(uint32_t seconds, uint32_t microseconds)
@@ -728,14 +728,20 @@ void system_pre_init(void)
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_2) = 0xFF;
 #if defined(CHIP_FAMILY_NPCX5)
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x0F; /* Skip GDMA */
-#elif defined(CHIP_FAMILY_NPCX7)
-	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x1F; /* Skip GDMA */
+#elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
+	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_3) = 0x3F; /* Skip GDMA */
 #endif
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_4) = 0xF4; /* Skip ITIM2/1_PD */
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8;
 
 	pwdwn6 = 0x70 |
+#if NPCX_FAMILY_VERSION <= NPCX_FAMILY_NPCX7
+		/*
+		 * Don't set PD of ITIM6 for NPCX9 and later chips because
+		 * they use it as the system timer.
+		 */
 		BIT(NPCX_PWDWN_CTL6_ITIM6_PD) |
+#endif
 		BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */
 #if !defined(CONFIG_HOSTCMD_ESPI)
 	pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD;
@@ -751,6 +757,9 @@ void system_pre_init(void)
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07;
 #endif
 #endif
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xFF;
+#endif
 
 	/* Following modules can be powered down automatically in npcx7 */
 #if defined(CHIP_FAMILY_NPCX5)
@@ -843,6 +852,7 @@ const char *system_get_chip_name(void)
 
 	/* Read Chip ID in core register */
 	uint8_t chip_id = NPCX_DEVICE_ID_CR;
+
 	switch (chip_id) {
 #if defined(CHIP_FAMILY_NPCX5)
 	case NPCX585G_CHIP_ID:
diff --git a/chip/npcx/system_chip.h b/chip/npcx/system_chip.h
index 2836a1e4f7..da98888787 100644
--- a/chip/npcx/system_chip.h
+++ b/chip/npcx/system_chip.h
@@ -65,8 +65,9 @@ extern unsigned int __flash_lplfw_start;
 
 /* End address for little FW; defined in linker script */
 extern unsigned int __flash_lplfw_end;
+#endif
 
-#elif defined(CHIP_FAMILY_NPCX7)
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7
 /* Configure PSL mode setting for the wake-up pins. */
 int system_config_psl_mode(enum gpio_signal signal);
 
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c
index 1e4d88f789..efe991ec0b 100644
--- a/chip/npcx/uart.c
+++ b/chip/npcx/uart.c
@@ -85,17 +85,34 @@ void npcx_gpio2uart(void)
 {
 #ifdef CONFIG_UART_PAD_SWITCH
 	if (pad == UART_ALTERNATE_PAD) {
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN__SL);
+		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL);
+		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL);
+		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL);
+#else
 		SET_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL);
 		CLEAR_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
+#endif
 		return;
 	}
 #endif
 
+#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9
+	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SIN_SL);
+	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SOUT_SL);
+	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SIN_SL);
+	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SOUT_SL);
+#else
 	SET_BIT(NPCX_UART_DEVALT, NPCX_UART_DEVALT_SL);
 	CLEAR_BIT(NPCX_UART_ALT_DEVALT, NPCX_UART_ALT_DEVALT_SL);
+#endif
 
-#if !NPCX_UART_MODULE2 && defined(CHIP_FAMILY_NPCX7)
-	/* UART module 1 belongs to KSO since wake-up functionality in npcx7. */
+#if !NPCX_UART_MODULE2 && (NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7)
+	/*
+	 * UART module 1 belongs to KSO since wake-up functionality in npcx7
+	 * and later chips.
+	 */
 	CLEAR_BIT(NPCX_DEVALT(0x09), NPCX_DEVALT9_NO_KSO09_SL);
 #endif
 }