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| author | Caveh Jalali <caveh@chromium.org> | 2020-10-16 00:54:16 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-11-19 20:52:54 +0000 |
| commit | 82a761da1b46229283672fb94ad617327d7149b1 (patch) | |
| tree | f9a54caed6969e1c834ebda0b54dade6dba21686 /chip/npcx | |
| parent | 7bd8d8b8e067bceda856902f0dc00c88d837847a (diff) | |
| download | chrome-ec-82a761da1b46229283672fb94ad617327d7149b1.tar.gz | |
npcx: avoid checking value of undefined symbol
This sets a default value of 0 for NPCX_UART_MODULE2 and
NPCX9_PWM1_SEL so that board files don't need to set these.
BRANCH=none
BUG=b:173575131
TEST=buildall
Change-Id: Ief84ed558bb5431f13fb01b963db3bd97fc8d659
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546639
Reviewed-by: CH Lin <chlin56@nuvoton.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'chip/npcx')
| -rw-r--r-- | chip/npcx/gpio_chip-npcx9.h | 4 | ||||
| -rw-r--r-- | chip/npcx/registers.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/chip/npcx/gpio_chip-npcx9.h b/chip/npcx/gpio_chip-npcx9.h index a80a1b899a..f07618317c 100644 --- a/chip/npcx/gpio_chip-npcx9.h +++ b/chip/npcx/gpio_chip-npcx9.h @@ -6,6 +6,10 @@ #ifndef __CROS_EC_GPIO_CHIP_NPCX9_H #define __CROS_EC_GPIO_CHIP_NPCX9_H +#ifndef NPCX9_PWM1_SEL +#define NPCX9_PWM1_SEL 0 +#endif /* NPCX9_PWM1_SEL */ + /*****************************************************************************/ /* Macro functions for MIWU mapping table */ diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 403d40b4a3..b9373cd659 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -1656,6 +1656,10 @@ extern enum gpio_signal hibernate_wake_pins[]; extern int hibernate_wake_pins_used; #endif +#ifndef NPCX_UART_MODULE2 +#define NPCX_UART_MODULE2 0 +#endif /* NPCX_UART_MODULE2 */ + #if defined(CHIP_FAMILY_NPCX5) #include "registers-npcx5.h" #elif defined(CHIP_FAMILY_NPCX7) |