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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-05-11 14:23:31 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-15 06:42:30 +0000 |
| commit | e3dce49334a2b44e337744bc719a27c63261f35e (patch) | |
| tree | 3ee485350fafffaf53206036a3a19184068feeb5 /chip/nrf51 | |
| parent | cba37a13d2342e4c81b0be3c84010baf3d846162 (diff) | |
| download | chrome-ec-e3dce49334a2b44e337744bc719a27c63261f35e.tar.gz | |
cleanup: Use appropriate image geometry CONFIGs
- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None
Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269
Diffstat (limited to 'chip/nrf51')
| -rw-r--r-- | chip/nrf51/config_chip.h | 21 |
1 files changed, 2 insertions, 19 deletions
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h index 104fceb0ca..78ee610601 100644 --- a/chip/nrf51/config_chip.h +++ b/chip/nrf51/config_chip.h @@ -41,33 +41,16 @@ /* Flash mapping */ #define CONFIG_FLASH_BASE 0x00000000 #define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000 -#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE #define CONFIG_FLASH_BANK_SIZE 0x1000 -/* Size of one firmware image in flash */ -#define CONFIG_FW_IMAGE_SIZE (128 * 1024) - -/* Define the RO/RW offset */ -#define CONFIG_RO_MEM_OFF 0 -#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE - -/* - * Put pstate after RO to give RW more space and make RO write protect - * region contiguous. - */ -#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE -#define CONFIG_FW_PSTATE_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE) - +#include "config_std_internal_flash.h" /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 32 /* Not that much RAM, set to smaller */ -#undef CONFIG_UART_TX_BUF_SIZE +#undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 1024 - #endif /* __CROS_EC_CONFIG_CHIP_H */ |