diff options
| author | Alec Berg <alecaberg@chromium.org> | 2014-07-22 10:17:45 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-07-23 18:35:42 +0000 |
| commit | c32c5571a51e5b191f423d451617a7dc902b9ad2 (patch) | |
| tree | d8a4d225eafdb8e83a16e77a54e7418e9d22fad0 /chip/stm32/adc-stm32f0.c | |
| parent | 205f6f6746c8a1788b93c7ce27ce62d0d6af02a5 (diff) | |
| download | chrome-ec-c32c5571a51e5b191f423d451617a7dc902b9ad2.tar.gz | |
samus_pd: stm32f0: check warm reboot before initializing ADC
Check for warm reboot before initializing ADC. Part of the initialization
process involves calibration of the ADC, which can only be done when the
ADC peripheral is disabled. This fixes a bug on samus_pd where jumping to
RW causes a watchdog because ADC reads hang.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=on samus_pd, without this change running sysjump rw causes us to jump
to RW and then causes a watchdog. With this change sysjump rw works. Also
verified that PD communication works in RW, which means ADC channels are
being read correctly after jumping to RW.
Change-Id: Iaa41da4795c3d15a6db56b0d715e36c29417d9b6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/209331
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/adc-stm32f0.c')
| -rw-r--r-- | chip/stm32/adc-stm32f0.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/chip/stm32/adc-stm32f0.c b/chip/stm32/adc-stm32f0.c index abf8830b6c..31c928fc6a 100644 --- a/chip/stm32/adc-stm32f0.c +++ b/chip/stm32/adc-stm32f0.c @@ -277,6 +277,13 @@ fail: static void adc_init(void) { + /* + * If clock is already enabled, then this is a warm reboot and + * ADC is already initialized. + */ + if (STM32_RCC_APB2ENR & (1 << 9)) + return; + /* Enable ADC clock */ STM32_RCC_APB2ENR |= (1 << 9); /* check HSI14 in RCC ? ON by default */ |