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| author | Moritz Fischer <moritz.fischer@ettus.com> | 2018-09-10 13:45:30 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-28 06:26:08 -0700 |
| commit | acfd14a3345e7b7fa3fd3520c5b399fe6229d3cc (patch) | |
| tree | a41ec808656f67abe2431aa1acff4f7f86875930 /chip/stm32/adc-stm32f3.c | |
| parent | 78ea73cde13cda17a9b6240cc0b288c95a2f6482 (diff) | |
| download | chrome-ec-acfd14a3345e7b7fa3fd3520c5b399fe6229d3cc.tar.gz | |
Make ADCs on STM32F4 work
Make ADCs on STM32F4 chips work by reusing most of the STM32F3 code
with the addition of SWSTART=1 bit in adc_read_channel.
The SWSTART=1 is most likely also required for the F3, but could
not be tested on actual hardware.
BUG=none
BRANCH=master
TEST=Build for nucleo-411RE and check measurements
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: Iea4f961b22119b5f2c1ee71295ec3ef1b7b7232c
Reviewed-on: https://chromium-review.googlesource.com/1217603
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Diffstat (limited to 'chip/stm32/adc-stm32f3.c')
| -rw-r--r-- | chip/stm32/adc-stm32f3.c | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/chip/stm32/adc-stm32f3.c b/chip/stm32/adc-stm32f3.c index 28a50916c6..6e22c49ac3 100644 --- a/chip/stm32/adc-stm32f3.c +++ b/chip/stm32/adc-stm32f3.c @@ -195,8 +195,12 @@ int adc_read_channel(enum adc_channel ch) /* Clear EOC bit */ STM32_ADC_SR &= ~(1 << 1); - /* Start conversion */ - STM32_ADC_CR2 |= (1 << 0); /* ADON */ + /* Start conversion (Note: For now only confirmed on F4) */ +#if defined(CHIP_FAMILY_STM32F4) + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON | STM32_ADC_CR2_SWSTART; +#else + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; +#endif /* Wait for EOC bit set */ deadline.val = get_time().val + ADC_SINGLE_READ_TIMEOUT; @@ -233,21 +237,21 @@ static void adc_init(void) if (!adc_powered()) { /* Power on ADC module */ - STM32_ADC_CR2 |= (1 << 0); /* ADON */ + STM32_ADC_CR2 |= STM32_ADC_CR2_ADON; /* Reset calibration */ - STM32_ADC_CR2 |= (1 << 3); /* RSTCAL */ - while (STM32_ADC_CR2 & (1 << 3)) + STM32_ADC_CR2 |= STM32_ADC_CR2_RSTCAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_RSTCAL) ; /* A/D Calibrate */ - STM32_ADC_CR2 |= (1 << 2); /* CAL */ - while (STM32_ADC_CR2 & (1 << 2)) + STM32_ADC_CR2 |= STM32_ADC_CR2_CAL; + while (STM32_ADC_CR2 & STM32_ADC_CR2_CAL) ; } /* Set right alignment */ - STM32_ADC_CR2 &= ~(1 << 11); + STM32_ADC_CR2 &= ~STM32_ADC_CR2_ALIGN; /* Set sample time of all channels */ STM32_ADC_SMPR1 = SMPR1_EXPAND(CONFIG_ADC_SAMPLE_TIME); |