Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-release

Generated by: ./util/update_release_branch.py --board bloonchipper --relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-fpmcu-bloonchipper-release

Relevant changes:

git log --oneline ad46fafb27..a46d3f3fea -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

981fb88cf8 docs/fingerprint: Resolve contradictory FPMCU factory flashing instructions
38ef6b7306 tree: Files should end with single newline
60032a8828 docs/fingerprint: Clean up formatting in fingerprint-factory-quick-guide.md
f49eb6f894 docs/fingerprint: Run mdformat
64aa5fc7bb docs/fingerprint: Add links to info on fuzz testing
8bd99cc434 fpsensor: Use correct return type
2b2d7a991d fpsensor: Use correct return type

BRANCH=None
BUG=b:234772776 b:234181908 b:172020503 b:234181908
TEST=`make -j buildall`

Cq-Include-Trybots: chromeos/cq:cq-orchestrator
Signed-off-by: Firas Sammoura <fsammoura@google.com>
Change-Id: I18b58de542c8b439d0f9327a7d4f0ec897da080f

1 files changed, 6 insertions, 11 deletions

diff --git a/chip/stm32/build.mk b/chip/stm32/build.mk
index 13a6aa752a..0d47a0131a 100644
--- a/chip/stm32/build.mk
+++ b/chip/stm32/build.mk
@@ -9,33 +9,28 @@
 ifeq ($(CHIP_FAMILY),stm32f0)
 # STM32F0xx sub-family has a Cortex-M0 ARM core
 CORE:=cortex-m0
-# Force ARMv6-M ISA used by the Cortex-M0
-# For historical reasons gcc calls it armv6s-m: ARM used to have ARMv6-M
-# without "svc" instruction, but that was short-lived. ARMv6S-M was the option
-# with "svc". GCC kept that naming scheme even though the distinction is long
-# gone.
-CFLAGS_CPU+=-march=armv6s-m -mcpu=cortex-m0
+CFLAGS_CPU+=-mcpu=cortex-m0
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32f3 stm32l4 stm32f4 \
 stm32g4))
 # STM32F3xx and STM32L4xx sub-family has a Cortex-M4 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M4 instruction set
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+CFLAGS_CPU+=-mcpu=cortex-m4
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32h7))
 # STM32FH7xx family has a Cortex-M7 ARM core
 CORE:=cortex-m
-# Allow the full Cortex-M4 instruction set (identical to M7)
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+# Allow the full Cortex-M7 instruction set.
+CFLAGS_CPU+=-mcpu=cortex-m7
 else ifeq ($(CHIP_FAMILY),$(filter $(CHIP_FAMILY),stm32l5))
 # STM32FL5xx family has a Cortex-M33 ARM core
 CORE:=cortex-m
 # Allow the full Cortex-M33 instruction set
-CFLAGS_CPU+=-march=armv8-m.main+dsp -mcpu=cortex-m33
+CFLAGS_CPU+=-mcpu=cortex-m33
 else
 # other STM32 SoCs have a Cortex-M3 ARM core
 CORE:=cortex-m
 # Force Cortex-M3 subset of instructions
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
+CFLAGS_CPU+=-mcpu=cortex-m3
 endif
 
 # Select between 16-bit and 32-bit timer for clock source