diff options
| author | Sam Hurst <shurst@google.com> | 2017-01-25 14:14:09 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-26 18:43:53 -0800 |
| commit | 90383450f6e12b409872c63875d33e58ab948906 (patch) | |
| tree | 012b0be5101317db4ac852222d843fb4081baa34 /chip/stm32/clock-stm32f0.c | |
| parent | 17515de32c7dffc5a9afd7e365a4dd31b3d3074a (diff) | |
| download | chrome-ec-90383450f6e12b409872c63875d33e58ab948906.tar.gz | |
usb: activate CRS on STM32F0
Enable the Clock Recovery Subsystem to automatically adjust the internal
HSI48 clock for proper USB operation on the STM32F0.
BUG=chrome-os-partner:34160
TEST=Manual testing on STM32F072B-DISCOVERY
Plugged in board and verified that device was detected with dmesg.
[1400698.702999] usb 3-10: new full-speed USB device number 47 using xhci_hcd
[1400698.720063] usb 3-10: New USB device found, idVendor=18d1, idProduct=500f
[1400698.720069] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[1400698.720072] usb 3-10: Product: PDeval-stm32f072
[1400698.720075] usb 3-10: Manufacturer: Google Inc.
BRANCH=none
Change-Id: I496a9a121a4b1a0009fe04cfe24aaa693ada9236
Reviewed-on: https://chromium-review.googlesource.com/433059
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index b94641ef0a..9f22388a27 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -179,6 +179,28 @@ defined(CHIP_VARIANT_STM32F070) * USB uses HSI48 = 48MHz */ +#ifdef CONFIG_USB + /* + * Configure and enable Clock Recovery System + * + * Since we are running from the internal RC HSI48 clock, the CSR + * is needed to guarantee an accurate 48MHz clock for USB. + * + * The default values configure the CRS to use the periodic USB SOF + * as the SYNC signal for calibrating the HSI48. + * + */ + + /* Enable Clock Recovery System */ + STM32_RCC_APB1ENR |= STM32_RCC_PB1_CRS; + + /* Enable automatic trimming */ + STM32_CRS_CR |= STM32_CRS_CR_AUTOTRIMEN; + + /* Enable oscillator clock for the frequency error counter */ + STM32_CRS_CR |= STM32_CRS_CR_CEN; +#endif + /* switch SYSCLK to HSI48 */ STM32_RCC_CFGR = 0x00000003; |