diff options
| author | Alec Berg <alecaberg@chromium.org> | 2014-09-25 09:34:01 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-09-29 23:18:44 +0000 |
| commit | a451aa850b72863d5a4fc0a0884bfb12780b2f32 (patch) | |
| tree | 552e82c7f101734a6444704635828a0bcdfb0bcb /chip/stm32/clock-stm32f0.c | |
| parent | 41b927442e770d6f2303d32f88a96b859775b27f (diff) | |
| download | chrome-ec-a451aa850b72863d5a4fc0a0884bfb12780b2f32.tar.gz | |
zinger: add low power stop mode
Add low power mode for zinger. This uses stop mode in task_wait_event(),
the non-runtime equivalent of the idle task.
BUG=chrome-os-partner:28335
BRANCH=samus
TEST=load onto zinger and plug and unplug into samus a bunch of times
to make sure it negotiates to 20V every time. also send custom vdm's
from samus_pd and make sure those always succeed.
Change-Id: I626365e7d22e030792d28dbf7eafaeb8f54f8a74
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219933
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
| -rw-r--r-- | chip/stm32/clock-stm32f0.c | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index b43a442f02..76583eaab0 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -108,8 +108,8 @@ static inline uint32_t sec_to_rtc(uint32_t sec) } /* Return time diff between two rtc readings */ -static inline int32_t get_rtc_diff(uint32_t rtc0, uint32_t rtc0ss, - uint32_t rtc1, uint32_t rtc1ss) +int32_t get_rtc_diff(uint32_t rtc0, uint32_t rtc0ss, + uint32_t rtc1, uint32_t rtc1ss) { int32_t diff; @@ -381,22 +381,8 @@ void clock_enable_module(enum module_id module, int enable) { } -void clock_init(void) +void rtc_init(void) { - /* - * The initial state : - * SYSCLK from HSI (=8MHz), no divider on AHB, APB1, APB2 - * PLL unlocked, RTC enabled on LSE - */ - - /* - * put 1 Wait-State for flash access to ensure proper reads at 48Mhz - * and enable prefetch buffer. - */ - STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; - - config_hispeed_clock(); - rtc_unlock_regs(); /* Enter RTC initialize mode */ @@ -420,6 +406,25 @@ void clock_init(void) rtc_lock_regs(); } +void clock_init(void) +{ + /* + * The initial state : + * SYSCLK from HSI (=8MHz), no divider on AHB, APB1, APB2 + * PLL unlocked, RTC enabled on LSE + */ + + /* + * put 1 Wait-State for flash access to ensure proper reads at 48Mhz + * and enable prefetch buffer. + */ + STM32_FLASH_ACR = STM32_FLASH_ACR_LATENCY | STM32_FLASH_ACR_PRFTEN; + + config_hispeed_clock(); + + rtc_init(); +} + /*****************************************************************************/ /* Console commands */ |