diff options
author | Vic Yang <victoryang@chromium.org> | 2014-10-22 10:01:44 -0700 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-10-22 21:50:44 +0000 |
commit | e26aedecf7e549a7081dd1a8e57e57474d60fe40 (patch) | |
tree | 5271e333f308bd9dbc1604c5b771d24a3677ae9d /chip/stm32/clock-stm32f0.c | |
parent | 0907881a3a87b4056c5debf56f64bf59cc3f7175 (diff) | |
download | chrome-ec-e26aedecf7e549a7081dd1a8e57e57474d60fe40.tar.gz |
Fix clock bug on STM32F0 that HSI48 isn't enabled
When changing the clock init code for STM32F3, I accidentally disabled
HSI48 for STM32F0, which is causing all problems on all STM32F0
platforms. Re-enable it.
BRANCH=Samus
BUG=chrome-os-partner:32660
TEST=Boot on Ryu P1 and see console.
Change-Id: Ie343cdb039d839e41b36489388fc91970e2bb7d8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/225002
Reviewed-by: Anatol Pomazau <anatol@google.com>
Tested-by: Anatol Pomazau <anatol@google.com>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'chip/stm32/clock-stm32f0.c')
-rw-r--r-- | chip/stm32/clock-stm32f0.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/chip/stm32/clock-stm32f0.c b/chip/stm32/clock-stm32f0.c index 0ef6489c86..39a18b8e09 100644 --- a/chip/stm32/clock-stm32f0.c +++ b/chip/stm32/clock-stm32f0.c @@ -230,7 +230,17 @@ static void config_hispeed_clock(void) /* Wait until the PLL is the clock source */ while ((STM32_RCC_CFGR & 0xc) != 0x8) ; -#elif (CPU_CLOCK == HSI48_CLOCK) +#else + /* Ensure that HSI48 is ON */ + if (!(STM32_RCC_CR2 & (1 << 17))) { + /* Enable HSI */ + STM32_RCC_CR2 |= 1 << 16; + /* Wait for HSI to be ready */ + while (!(STM32_RCC_CR2 & (1 << 17))) + ; + } + +#if (CPU_CLOCK == HSI48_CLOCK) /* * HSI48 = 48MHz, no prescaler, no MCO, no PLL * therefore PCLK = FCLK = SYSCLK = 48MHz @@ -277,7 +287,8 @@ static void config_hispeed_clock(void) ; #else -#error "CPU_CLOCK must be either 48MHz or 38.4MHz for STM32F0" +#error "CPU_CLOCK must be either 48MHz or 38.4MHz" +#endif #endif } |